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+ // SPDX-FileCopyrightText: 2020 Efabless Corporation
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+ //
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+ // Licensed under the Apache License, Version 2.0 (the "License");
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+ // you may not use this file except in compliance with the License.
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+ // You may obtain a copy of the License at
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+ //
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+ // http://www.apache.org/licenses/LICENSE-2.0
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+ //
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+ // Unless required by applicable law or agreed to in writing, software
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+ // distributed under the License is distributed on an "AS IS" BASIS,
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+ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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+ // See the License for the specific language governing permissions and
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+ // limitations under the License.
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+ // SPDX-License-Identifier: Apache-2.0
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+
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+ `default_nettype none
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+
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+ `include "example_por.v"
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+
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+ /*
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+ * I/O mapping for analog
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+ *
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+ * mprj_io[37] io_in/out/oeb/in_3v3[26] --- ---
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+ * mprj_io[36] io_in/out/oeb/in_3v3[25] --- ---
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+ * mprj_io[35] io_in/out/oeb/in_3v3[24] gpio_analog/noesd[17] ---
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+ * mprj_io[34] io_in/out/oeb/in_3v3[23] gpio_analog/noesd[16] ---
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+ * mprj_io[33] io_in/out/oeb/in_3v3[22] gpio_analog/noesd[15] ---
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+ * mprj_io[32] io_in/out/oeb/in_3v3[21] gpio_analog/noesd[14] ---
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+ * mprj_io[31] io_in/out/oeb/in_3v3[20] gpio_analog/noesd[13] ---
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+ * mprj_io[30] io_in/out/oeb/in_3v3[19] gpio_analog/noesd[12] ---
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+ * mprj_io[29] io_in/out/oeb/in_3v3[18] gpio_analog/noesd[11] ---
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+ * mprj_io[28] io_in/out/oeb/in_3v3[17] gpio_analog/noesd[10] ---
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+ * mprj_io[27] io_in/out/oeb/in_3v3[16] gpio_analog/noesd[9] ---
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+ * mprj_io[26] io_in/out/oeb/in_3v3[15] gpio_analog/noesd[8] ---
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+ * mprj_io[25] io_in/out/oeb/in_3v3[14] gpio_analog/noesd[7] ---
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+ * mprj_io[24] --- --- user_analog[10]
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+ * mprj_io[23] --- --- user_analog[9]
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+ * mprj_io[22] --- --- user_analog[8]
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+ * mprj_io[21] --- --- user_analog[7]
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+ * mprj_io[20] --- --- user_analog[6] clamp[2]
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+ * mprj_io[19] --- --- user_analog[5] clamp[1]
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+ * mprj_io[18] --- --- user_analog[4] clamp[0]
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+ * mprj_io[17] --- --- user_analog[3]
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+ * mprj_io[16] --- --- user_analog[2]
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+ * mprj_io[15] --- --- user_analog[1]
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+ * mprj_io[14] --- --- user_analog[0]
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+ * mprj_io[13] io_in/out/oeb/in_3v3[13] gpio_analog/noesd[6] ---
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+ * mprj_io[12] io_in/out/oeb/in_3v3[12] gpio_analog/noesd[5] ---
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+ * mprj_io[11] io_in/out/oeb/in_3v3[11] gpio_analog/noesd[4] ---
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+ * mprj_io[10] io_in/out/oeb/in_3v3[10] gpio_analog/noesd[3] ---
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+ * mprj_io[9] io_in/out/oeb/in_3v3[9] gpio_analog/noesd[2] ---
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+ * mprj_io[8] io_in/out/oeb/in_3v3[8] gpio_analog/noesd[1] ---
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+ * mprj_io[7] io_in/out/oeb/in_3v3[7] gpio_analog/noesd[0] ---
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+ * mprj_io[6] io_in/out/oeb/in_3v3[6] --- ---
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+ * mprj_io[5] io_in/out/oeb/in_3v3[5] --- ---
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+ * mprj_io[4] io_in/out/oeb/in_3v3[4] --- ---
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+ * mprj_io[3] io_in/out/oeb/in_3v3[3] --- ---
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+ * mprj_io[2] io_in/out/oeb/in_3v3[2] --- ---
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+ * mprj_io[1] io_in/out/oeb/in_3v3[1] --- ---
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+ * mprj_io[0] io_in/out/oeb/in_3v3[0] --- ---
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+ *
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+ */
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+
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+ /*
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+ *----------------------------------------------------------------
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+ *
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+ * user_analog_proj_example
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+ *
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+ * This is an example of a (trivially simple) analog user project,
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+ * showing how the user project can connect to the I/O pads, both
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+ * the digital pads, the analog connection on the digital pads,
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+ * and the dedicated analog pins used as an additional power supply
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+ * input, with a connected ESD clamp.
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+ *
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+ * See the testbench in directory "mprj_por" for the example
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+ * program that drives this user project.
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+ *
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+ *----------------------------------------------------------------
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+ */
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+
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+ module user_analog_proj_example (
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+ `ifdef USE_POWER_PINS
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+ inout vdda1, // User area 1 3.3V supply
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+ inout vdda2, // User area 2 3.3V supply
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+ inout vssa1, // User area 1 analog ground
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+ inout vssa2, // User area 2 analog ground
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+ inout vccd1, // User area 1 1.8V supply
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+ inout vccd2, // User area 2 1.8v supply
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+ inout vssd1, // User area 1 digital ground
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+ inout vssd2, // User area 2 digital ground
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+ `endif
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+
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+ // Wishbone Slave ports (WB MI A)
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+ input wb_clk_i,
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+ input wb_rst_i,
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+ input wbs_stb_i,
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+ input wbs_cyc_i,
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+ input wbs_we_i,
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+ input [3:0] wbs_sel_i,
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+ input [31:0] wbs_dat_i,
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+ input [31:0] wbs_adr_i,
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+ output wbs_ack_o,
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+ output [31:0] wbs_dat_o,
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+
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+ // Logic Analyzer Signals
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+ input [127:0] la_data_in,
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+ output [127:0] la_data_out,
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+ input [127:0] la_oenb,
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+
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+ // IOs
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+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
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+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
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+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
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+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
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+
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+ // GPIO-analog
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+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
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+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
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+
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+ // Dedicated analog
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+ inout [`ANALOG_PADS-1:0] io_analog,
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+ inout [2:0] io_clamp_high,
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+ inout [2:0] io_clamp_low,
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+
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+ // Clock
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+ input user_clock2,
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+
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+ // IRQ
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+ output [2:0] irq
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+ );
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+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;
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+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;
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+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;
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+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;
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+ wire [`ANALOG_PADS-1:0] io_analog;
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+
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+ // wire [31:0] rdata;
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+ // wire [31:0] wdata;
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+
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+ // wire valid;
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+ // wire [3:0] wstrb;
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+
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+ wire isupply; // Independent 3.3V supply
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+ wire io16, io15, io12, io11;
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+
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+ // WB MI A
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+ // assign valid = wbs_cyc_i && wbs_stb_i;
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+ // assign wstrb = wbs_sel_i & {4{wbs_we_i}};
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+ // assign wbs_dat_o = rdata;
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+ // assign wdata = wbs_dat_i;
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+
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+ // IO --- unused (no need to connect to anything)
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+ // assign io_out[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = 0;
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+ // assign io_out[14:13] = 11'b0;
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+ // assign io_out[10:0] = 11'b0;
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+
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+ // assign io_oeb[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = -1;
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+ // assign io_oeb[14:13] = 11'b1;
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+ // assign io_oeb[10:0] = 11'b1;
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+
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+ // IO --- enable outputs on 11, 12, 15, and 16
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+ assign io_out[12:11] = {io12, io11};
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+ assign io_oeb[12:11] = {vssd1, vssd1};
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+
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+ assign io_out[16:15] = {io16, io15};
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+ assign io_oeb[16:15] = {vssd1, vssd1};
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+
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+ // IRQ
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+ assign irq = 3'b000; // Unused
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+
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+ // LA --- unused (no need to connect to anything)
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+ // assign la_data_out = {128{1'b0}}; // Unused
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+
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+ // Instantiate the POR. Connect the digital power to user area 1
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+ // VCCD, and connect the analog power to user area 1 VDDA.
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+
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+ // Monitor the 3.3V output with mprj_io[10] = gpio_analog[3]
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+ // Monitor the 1.8V outputs with mprj_io[11,12] = io_out[11,12]
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+
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+ example_por por1 (
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+ `ifdef USE_POWER_PINS
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+ .vdd3v3(vdda1),
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+ .vdd1v8(vccd1),
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+ .vss(vssa1),
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+ `endif
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+ .porb_h(gpio_analog[3]), // 3.3V domain output
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+ .porb_l(io11), // 1.8V domain output
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+ .por_l(io12) // 1.8V domain output
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+ );
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+
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+ // Instantiate 2nd POR with the analog power supply on one of the
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+ // analog pins. NOTE: io_analog[4] = mproj_io[18] and is the same
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+ // pad with io_clamp_high/low[0].
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+
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+ `ifdef USE_POWER_PINS
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+ assign isupply = io_analog[4];
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+ assign io_clamp_high[0] = isupply;
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+ assign io_clamp_low[0] = vssa1;
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+
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+ // Tie off remaining clamps
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+ assign io_clamp_high[2:1] = vssa1;
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+ assign io_clamp_low[2:1] = vssa1;
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+ `endif
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+
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+ // Monitor the 3.3V output with mprj_io[25] = gpio_analog[7]
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+ // Monitor the 1.8V outputs with mprj_io[26,27] = io_out[15,16]
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+
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+ example_por por2 (
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+ `ifdef USE_POWER_PINS
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+ .vdd3v3(isupply),
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+ .vdd1v8(vccd1),
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+ .vss(vssa1),
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+ `endif
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+ .porb_h(gpio_analog[7]), // 3.3V domain output
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+ .porb_l(io15), // 1.8V domain output
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+ .por_l(io16) // 1.8V domain output
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+ );
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+
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+ endmodule
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+
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+ `default_nettype wire
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