This is a LDPC Project for 5g lower matrix

LDPC_Project

LDPC Project is a sample smaller version of the design that is optimized using a SRAM to have low area. This increases the simulation time, as every iteration takes more number of clocks to do one step at a time, but it is still fast enough to correct errors. It takes 5,515,887,500ps 5ms to complete the task of correcting errors for a LDPC(208,168,40) codeblock at clock frequency of 40MHz.

The design for 5 clocks per iteration, with upto maximum required loops of 12 the number of clocks required are 60 clocks, at a clock which can be as fast as 1.2 GHz or more.

The slower design is for proof of concept, though can be used for 5G. For 6G the same matrices can be used with the faster design to get high throughput.

The matrices for 5G,6G are...

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ENV setup

env.bash env.tcsh

Project Structure

module git@github.com:manish03/LDPCENCDEC.git sub modules: git@github.com:rggen/rggen-verilog-rtl.git git@github.com:mattvenn/openlane_summary.git git@repositories.efabless.com:manishmahajan/LDPC_ENC_DEC.git

Simulation can be run using the script

LDPCENCDEC/run.sh

For Synthesis use the script

Makefile in LDPCENCDEC/openlane/

ip_files

are present in the LDPCENCDEC/verilog/rtl directory.

design files

are present in LDPCENCDEC/verilog/rtl/LDPC_ENC_DEC directory

NOTE: Current design file examples are provided for initial reference. These files are currently being updated and will be reposted once complete. The simulations are working, gds has been created successfully.

C Program sample

A C program with an example for stimulus which will be encoded, error insertion and decoding has been provided at LDPCENCDEC/verilog/dv/wb_port/wb_port.c