Files
README.md
Mirafra SW Technologies Pvt. Ltd
This is a private project
| user_proj_example | . |
|---|---|
| design_name | user_proj_example |
| config | 24_05_30_11_11 |
| flow_status | flow completed |
| total_runtime | 1h51m26s0ms |
| routed_runtime | 1h23m15s0ms |
| (Cell/mm^2)/Core_Util | 3910.423536 |
| DIEAREA_mm^2 | 8.9424 |
| CellPer_mm^2 | 2737.296475 |
| OpenDP_Util | 3.35 |
| Final_Util | -1 |
| Peak_Memory_Usage_MB | 11447.27 |
| synth_cell_count | 22591 |
| tritonRoute_violations | 0 |
| Short_violations | 0 |
| MetSpc_violations | 0 |
| OffGrid_violations | 0 |
| MinHole_violations | 0 |
| Other_violations | 0 |
| Magic_violations | 0 |
| pin_antenna_violations | 16 |
| net_antenna_violations | 16 |
| lvs_total_errors | 0 |
| cvc_total_errors | -1 |
| klayout_violations | -1 |
| wire_length | 1390654 |
| vias | 187841 |
| wns | 0 |
| pl_wns | -1 |
| optimized_wns | -1 |
| fastroute_wns | -1 |
| spef_wns | 0 |
| tns | 0 |
| pl_tns | -1 |
| optimized_tns | -1 |
| fastroute_tns | -1 |
| spef_tns | 0 |
| HPWL | 1144989518 |
| routing_layer1_pct | 0 |
| routing_layer2_pct | 4.18 |
| routing_layer3_pct | 4.33 |
| routing_layer4_pct | 0.34 |
| routing_layer5_pct | 0.26 |
| routing_layer6_pct | -1 |
| wires_count | 22120 |
| wire_bits | 34954 |
| public_wires_count | 1173 |
| public_wire_bits | 14007 |
| memories_count | 0 |
| memory_bits | 0 |
| processes_count | 0 |
| cells_pre_abc | 21652 |
| AND | 676 |
| DFF | 1 |
| NAND | 506 |
| NOR | 1743 |
| OR | 3773 |
| XOR | 1998 |
| XNOR | 1271 |
| MUX | 3459 |
| inputs | 568 |
| outputs | 763 |
| level | 169 |
| DecapCells | 631242 |
| WelltapCells | 126202 |
| DiodeCells | 15256 |
| FillCells | 139237 |
| NonPhysCells | 24478 |
| TotalCells | 936415 |
| CoreArea_um^2 | 8845493.53 |
| power_slowest_internal_uW | -1 |
| power_slowest_switching_uW | -1 |
| power_slowest_leakage_uW | -1 |
| power_typical_internal_uW | 0.0128 |
| power_typical_switching_uW | 0.0309 |
| power_typical_leakage_uW | 5.67E-07 |
| power_fastest_internal_uW | -1 |
| power_fastest_switching_uW | -1 |
| power_fastest_leakage_uW | -1 |
| critical_path_ns | 27.72 |
| suggested_clock_period | 25 |
| suggested_clock_frequency | 40 |
| CLOCK_PERIOD | 25 |
| FP_ASPECT_RATIO | 1 |
| FP_CORE_UTIL | 70 |
| FP_PDN_HPITCH | 153.18 |
| FP_PDN_VPITCH | 153.6 |
| GRT_ADJUSTMENT | 0.2 |
| GRT_REPAIR_ANTENNAS | 1 |
| MAX_FANOUT_CONSTRAINT | 16 |
| PL_TARGET_DENSITY | 0.3 |
| RUN_HEURISTIC_DIODE_INSERTION | 1 |
| STD_CELL_LIBRARY | sky130_fd_sc_hd |
| SYNTH_STRATEGY | AREA 3 |
##############################################################
| user_project_wrapper | . |
|---|---|
| design_name | user_project_wrapper |
| config | 24_05_30_13_17 |
| flow_status | flow completed |
| total_runtime | 0h42m9s0ms |
| routed_runtime | 0h5m50s0ms |
| (Cell/mm^2)/Core_Util | 0.194582814 |
| DIEAREA_mm^2 | 10.2784 |
| CellPer_mm^2 | 0.097291407 |
| OpenDP_Util | -1 |
| Final_Util | -1 |
| Peak_Memory_Usage_MB | 593.81 |
| synth_cell_count | 1 |
| tritonRoute_violations | 0 |
| Short_violations | 0 |
| MetSpc_violations | 0 |
| OffGrid_violations | 0 |
| MinHole_violations | 0 |
| Other_violations | 0 |
| Magic_violations | 0 |
| pin_antenna_violations | 155 |
| net_antenna_violations | 155 |
| lvs_total_errors | 0 |
| cvc_total_errors | -1 |
| klayout_violations | -1 |
| wire_length | 147091 |
| vias | 1260 |
| wns | 0 |
| pl_wns | -1 |
| optimized_wns | -1 |
| fastroute_wns | -1 |
| spef_wns | 0 |
| tns | 0 |
| pl_tns | -1 |
| optimized_tns | -1 |
| fastroute_tns | -1 |
| spef_tns | 0 |
| HPWL | -1 |
| routing_layer1_pct | 0 |
| routing_layer2_pct | 0.18 |
| routing_layer3_pct | 4.48 |
| routing_layer4_pct | 1.77 |
| routing_layer5_pct | 0.39 |
| routing_layer6_pct | -1 |
| wires_count | 19 |
| wire_bits | 637 |
| public_wires_count | 19 |
| public_wire_bits | 637 |
| memories_count | 0 |
| memory_bits | 0 |
| processes_count | 0 |
| cells_pre_abc | 1 |
| AND | 0 |
| DFF | 0 |
| NAND | 0 |
| NOR | 0 |
| OR | 0 |
| XOR | 0 |
| XNOR | 0 |
| MUX | 0 |
| inputs | -1 |
| outputs | -1 |
| level | -1 |
| DecapCells | 0 |
| WelltapCells | 0 |
| DiodeCells | 0 |
| FillCells | 0 |
| NonPhysCells | 1 |
| TotalCells | 1 |
| CoreArea_um^2 | 10173980.15 |
| power_slowest_internal_uW | -1 |
| power_slowest_switching_uW | -1 |
| power_slowest_leakage_uW | -1 |
| power_typical_internal_uW | 0.0128 |
| power_typical_switching_uW | 0.031 |
| power_typical_leakage_uW | 5.67E-07 |
| power_fastest_internal_uW | -1 |
| power_fastest_switching_uW | -1 |
| power_fastest_leakage_uW | -1 |
| critical_path_ns | 27.8 |
| suggested_clock_period | 25 |
| suggested_clock_frequency | 40 |
| CLOCK_PERIOD | 25 |
| FP_ASPECT_RATIO | 1 |
| FP_CORE_UTIL | 50 |
| FP_PDN_HPITCH | 180 |
| FP_PDN_VPITCH | 180 |
| GRT_ADJUSTMENT | 0.3 |
| GRT_REPAIR_ANTENNAS | 0 |
| MAX_FANOUT_CONSTRAINT | 10 |
| PL_TARGET_DENSITY | 0.6 |
| RUN_HEURISTIC_DIODE_INSERTION | 0 |
| STD_CELL_LIBRARY | sky130_fd_sc_hd |
| SYNTH_STRATEGY | AREA 0 |
##############################################################