Efabless Repositories

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Includes 3 different IPs; PSRAM controller,...

created 11 months ago

AES accelerator example connected on the WB bus

created 11 months ago

Blizzard includes CAN controller - SAR ADC -...

created a year ago

Caravel with DFT in the SoC and user project wrapper

created 3 weeks ago

Caravel DFT with AES user project wrapper from...

created 2 weeks ago

A Machine Learning Demonstration SoC

created 6 months ago

CLEAR is an Open Source FPGA-ASIC utilizing 9x9 eFPGA

created a year ago

Counter user project example using OpenLane 2

created 8 months ago

A test chip including three 3.3 V to 1.8 V, 100 mA, LDO

created a year ago

A test chip including three 3.3 V to 1.8 V,...

created 11 months ago

Cheetah: A test chip for an ML demonstrator SoC.

created 8 months ago

Multi-Project Caravel (MPC): The user’s...

created a year ago

Test chip for S8TSSC

created 3 weeks ago

Swift redesign

created 2 weeks ago