mshalan

burak_aykenar/SAKAv0.1

This is an embedded FPGA (eFPGA) IP project. The fabric netlist is generated by OpenFPGA framework. https://github.com/lnis-uofu/OpenFPGA This IP is designed by Yongatek Microelectronics. Yongatek Microelectronics provide a wide range of IC/ASIC/SoC/Chip Design, 5G/6G and Satellite Communications, Video Processing and IoT areas within the industry with an experienced and highly qualified R&D team. https://www.yongatek.com/ FPGA fabric consist of 6x6 complex logic blocks (CLB). Each CLB has 4 logic elements (LE). Each logic element has a LUT4 and a FF. Routing channels have 60 tracks: 6 L1, 6 L2 and 48 L4 track lengths. There are 24 IO blocks surrounding the fabric. Each IOB has 6 IO pins, a total of 144 pins. Pins are connected to logic analyzer (LA) of the management core and other 38 external IOs. You can contact through info@yongatek.com

christoph/ScoooterDexie

A security hardened RISC-V processor.

monktech/Smowcode

Smowcode – An industry-grade visual coding language for ESP32 & MSPM0+ micro-controllers.

efabless_common/snappy_tapeout

Snappy Project Tapeout

ymei/SNRLxP0

SNRLxP0 chip for efabless tapeout in sky130

tbeechem/SpecereThermVeh

This is a thermal test vehicle designed to assess optical thermometry methods and their applicability to logic.

passant/SRAM-TC

Test chip for S8TSSC

engrvip/ssp_testchip

This is the first testchip containing designs from KACST-SSP students.

passant/swift-V3

Swift redesign

samdlarson/test_chip_B_231105

Bare Die Version - Test Chip

samdlarson/test_chip_PV_231105

Packaged Version - Test Chip

niorcasitas07/UNIC-CASS_Ring_Oscillators

This repository includes the files related to the proposal entitled ‘Ring Oscillators Frequency degradation for Reliability characterization with Bias temperature instability (BTI) and hot carrier (HC) effects’ for UNICASS 2024.

ryanmprice/UTEP_CML_Sensor_Test_Article_17

Convergent Microsystems Lab Test article for sensor interfaces

a_aboulsaad/UW-EE437-SP24

This is a capstone course project led by Professor Jacques C. Rudell, along with the PhD candidate Ahmed R. Aboulsaad. The tape-out chip will include 4 projects designed by undergraduate students and graduate students: 1- Quantum Controller Receiver Project. 2- Audio Amplifier Project. 3- Bi-directional Wireline Chip Interface Project. 4- High Linearity N-Path Filter Project.

elpidakrp/UW-elpida

UW-elpida

vonbraunlabs/vbl-riscv-ci2406

VBL RISC-V

vonbraunlabs/vbl_riscv_slx

von Braun Labs RISC-V

vonbraunlabs/vbl-riscv-slx

von Braun Labs - RISCV

Projects