eduholg
USFQ • Joined a year ago
Top Projects
eduholg/UNIC-CASS-555_Timer_PWM_Controller_Circuit
Development of an ASIC with an integrated timing circuit architecture inspired by the well-established 555 timer. The ASIC will be designed to function both as a Clock Generator and a Pulse-Width Modulator (PWM), addressing the need for reliable timing solutions in integrated circuits. Utilizing an open-source Process Design Kit (PDK), the project seeks to offer a flexible and cost-effective design that can be adapted for multiple ASIC applications. The design process will emphasize high precision, stability, and versatility, ensuring the ASIC can cater to a range of electronic systems requiring accurate timing and signal modulation.
eduholg/UNIC-CASS-Agro_Chip
The IC is intended to be an ASIC designed to determine banana plants health and the presence of banana weevils within the banana corm in a non-invasive way. The evaluation of the plant’s health will be determined by a sap flow sensor, whereas the presence of weevils will be determined by an ultrasonic microphone discriminating the 1.4kHz to 2.6kHz frequency band within the sensor’s wide range. The design of the IC will include a Band Pass Filter and two ADCs with a controller which will include two clock dividers, two comparators and a serializer. The serialized output of the chip then will pass through a serial to RF stage to further send the information to a monitoring station. The controller of the IC will be governed by a main clock signal with clock dividers to perform serialization and processing data obtained by the signal of the sensor once passed through the ADC. The updating of the output will be performed twice a day for 2 minutes during day and night for 4 attempts.