Arithmatic Logic Unit ALU is a processor unit which performs the task of addition, subtraction, multiplication, and division. In order to support CPU for its arithmatic and logical processes, ALU has AU (i.e) arithmatic unit and LU (i.e) Logical Unit. This paper deals with its analysis and functioning of this important unit of CPU using verilog. Introduction An arithmatic logic unit is an important part of central processing unit and performs arithmatic and logic operations. It can take inputs as multiple bits through an input register. It is the fundamental building block of the central processing unit of a computer.The ALU is the mathematical brain of a computer. The first ALU was INTEL 74181 implemented as a 7400 series is a TTL integrated circuit that was released in 1970.[1] Description This is a ALU model which receives two input operands ’A’ and ’B’ which are 8 bits long. The result is denoted by ’R’ which is also 8 bit long. The input signal ’Op’ is a 3 bit value which tells the ALU what operation has to be performed by the ALU. Since ’Op’ is 3 bits long we can have a maximum of 2 3 = 8operations.[2] ALU This ALU is capable of doing the following operations: Add Signed : R = A + B ( Treating A, B, and R as signed two’s complement integers.) Subtract Signed : R = A - B (Treating A, B, and R as signed two’s complement integers.) Bitwise AND : R(i) = A(i) AND B(i). Bitwise NOR : R(i) = A(i) NOR B(i). Bitwise OR : R(i) = A(i) OR B(i). Bitwise NAND : R(i) = A(i) NAND B(i). Bitwise XOR : R(i) = A(i) XOR B(i). Biwise NOT : R(i) = NOT A(i). BasicBlockDiagram Applications Processor Applications Logical calculations Arithmatic Calculations About iverilog Icarus Verilog is an implementation of the Verilog hardware description language. About GTKWave GTKWave is a fully featured GTK+ v1. 2 based wave viewer for Unix and Win32 which reads Ver Structural Verilog Compiler generated AET files as well as standard Verilog VCD/EVCD files and allows their viewing Installing iverilog and GTKWave For Ubuntu Open your terminal and type the following to install iverilog and GTKWave $ sudo apt-get update $ sudo apt-get install iverilog gtkwave Functional Simulation To clone the Repository and download the Netlist files for Simulation, enter the following commands in your terminal. $ sudo apt install -y git $ git clone https://https://github.com/aashish-tiwary/ALU $ cd iiitb_ALU $ iverilog iiitb_ALU.v iiitb_module_tb_alu.v $ ./a.out $ gtkwave ALU.vcd Functional Characteristics ALU_sim Synthesis Synthesis: Synthesis transforms the simple RTL design into a gate-level netlist with all the constraints as specified by the designer. In simple language, Synthesis is a process that converts the abstract form of design to a properly implemented chip in terms of logic gates. Synthesis takes place in multiple steps: Converting RTL into simple logic gates. Mapping those gates to actual technology-dependent logic gates available in the technology libraries. Optimizing the mapped netlist keeping the constraints set by the designer intact. Synthesizer: It is a tool we use to convert out RTL design code to netlist. Yosys is the tool I've used in this project. About Yosys Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. more at https://yosyshq.net/yosys/ To install yosys follow the instructions in this github repository https://github.com/YosysHQ/yosys Now you need to create a yosys_run.sh file , which is the yosys script file used to run the synthesis. The contents of the yosys_run file are given below: note: Identify the .lib file path in cloned folder and change the path in highlighted text to indentified path # read design read_verilog iiitb_alu.v # generic synthesis synth -top iiitb_alu # mapping to mycells.lib dfflibmap -liberty /home/aashish/asic/lib/sky130_fd_sc_hd__tt_025C_1v80.lib abc -liberty /home/aashish/asic/lib/sky130_fd_sc_hd__tt_025C_1v80.lib -script +strash;scorr;ifraig;retime,{D};strash;dch,-f;map,-M,1,{D} clean flatten # write synthesized design write_verilog -noattr iiitb_alu_synth.v show stat Now, in the terminal of your verilog files folder, run the following commands: to synthesize $ yosys $ yosys> script yosys_run.sh to see diffarent types of cells after synthesys $ yosys> stat to generate schematics $ yosys> show Now the synthesized netlist is written in "iiitb_alu_synth.v" file. GATE LEVEL SIMULATION(GLS) GLS is generating the simulation output by running test bench with netlist file generated from synthesis as design under test. Netlist is logically same as RTL code, therefore, same test bench can be used for it.We perform this to verify logical correctness of the design after synthesizing it. Also ensuring the timing of the design is met. Folllowing are the commands to run the GLS simulation: iverilog -DFUNCTIONAL -DUNIT_DELAY=#1 primitives.v sky130_fd_sc_hd.v iiitb_alu_synth.v iiitb_alu_tb.v The gtkwave output for the netlist should match the output waveform for the RTL design file. As netlist and design code have same set of inputs and outputs, we can use the same testbench and compare the waveforms. GLS Waveforms Gls Waveform Advance Physical Design Using OpenLANE/Sky130 OpenLANE is an opensource tool or flow used for opensource tape-outs. The OpenLANE flow comprises a variety of tools such as Yosys, ABC, OpenSTA, Fault, OpenROAD app, Netgen and Magic which are used to harden chips and macros, i.e. generate final GDSII from the design RTL. The primary goal of OpenLANE is to produce clean GDSII with no human intervention. OpenLANE has been tuned to function for the Google-Skywater130 Opensource Process Design Kit. SoC Design & OpenLANE Components of opensource digital ASIC design The design of digital Application Specific Integrated Circuit (ASIC) requires three enablers or elements - Resistor Transistor Logic Intellectual Property (RTL IPs), Electronic Design Automation (EDA) Tools and Process Design Kit (PDK) data. image Opensource RTL Designs: github, librecores, opencores Opensource EDA tools: QFlow, OpenROAD, OpenLANE Opensource PDK data: Google Skywater130 PDK The ASIC flow objective is to convert RTL design to GDSII format used for final layout. The flow is essentially a software also known as automated PnR (Place & route). This project is done in the course "Advanced Physical Design using OpenLANE/Sky130" by VLSI System Design Corporation. In this project a complete RTL to GDSII flow for PicoRV32a SoC is executed with Openlane using Skywater130nm PDK. Custom designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisations are carried out. Slack violations are removed. DRC is verified. image Synthesis: RTL Converted to gate level netlist using standard cell libraries (SCL) Floor & Power Planning: Planning of silicon area to ensure robust power distribution Placement: Placing cells on floorplan rows aligned with sites Global Placement: for optimal position of cells Detailed Placement: for legal positions Routing: Valid patterns for wires Signoff: Physical (DRC, LVS) and Timing verifications (STA) OpenLANE ASIC Flow image From conception to product, the ASIC design flow is an iterative process that is not static for every design. The details of the flow may change depending on ECO’s, IP requirements, DFT insertion, and SDC constraints, however the base concepts still remain. The flow can be broken down into 11 steps: Architectural Design – A system engineer will provide the VLSI engineer with specifications for the system that are determined through physical constraints. The VLSI engineer will be required to design a circuit that meets these constraints at a microarchitecture modeling level. RTL Design/Behavioral Modeling – RTL design and behavioral modeling are performed with a hardware description language (HDL). EDA tools will use the HDL to perform mapping of higher-level components to the transistor level needed for physical implementation. HDL modeling is normally performed using either Verilog or VHDL. One of two design methods may be employed while creating the HDL of a microarchitecture: a. RTL Design – Stands for Register Transfer Level. It provides an abstraction of the digital circuit using: * i. Combinational logic * ii. Registers * iii. Modules (IP’s or Soft Macros) b. Behavioral Modeling – Allows the microarchitecture modeling to be performed with behavior-based modeling in HDL. This method bridges the gap between C and HDL allowing HDL design to be performed RTL Verification - Behavioral verification of design DFT Insertion - Design-for-Test Circuit Insertion Logic Synthesis – Logic synthesis uses the RTL netlist to perform HDL technology mapping. The synthesis process is normally performed in two major steps: GTECH Mapping – Consists of mapping the HDL netlist to generic gates what are used to perform logical optimization based on AIGERs and other topologies created from the generic mapped netlist. Technology Mapping – Consists of mapping the post-optimized GTECH netlist to standard cells described in the PDK Sandard Cells – Standard cells are fixed height and a multiple of unit size width. This width is an integer multiple of the SITE size or the PR boundary. Each standard cell comes with SPICE, HDL, liberty, layout (detailed and abstract) files used by different tools at different stages in the RTL2GDS flow. Post-Synthesis STA Analysis: Performs setup analysis on different path groups. Floorplanning – Goal is to plan the silicon area and create a robust power distribution network (PDN) to power each of the individual components of the synthesized netlist. In addition, macro placement and blockages must be defined before placement occurs to ensure a legalized GDS file. In power planning we create the ring which is connected to the pads which brings power around the edges of the chip. We also include power straps to bring power to the middle of the chip using higher metal layers which reduces IR drop and electro-migration problem. Placement – Place the standard cells on the floorplane rows, aligned with sites defined in the technology lef file. Placement is done in two steps: Global and Detailed. In Global placement tries to find optimal position for all cells but they may be overlapping and not aligned to rows, detailed placement takes the global placement and legalizes all of the placements trying to adhere to what the global placement wants. CTS – Clock tree synteshsis is used to create the clock distribution network that is used to deliver the clock to all sequential elements. The main goal is to create a network with minimal skew across the chip. H-trees are a common network topology that is used to achieve this goal. Routing – Implements the interconnect system between standard cells using the remaining available metal layers after CTS and PDN generation. The routing is performed on routing grids to ensure minimal DRC errors. Opensource EDA tools OpenLANE utilises a variety of opensource tools in the execution of the ASIC flow: image OpenLANE design stages Synthesis yosys - Performs RTL synthesis abc - Performs technology mapping OpenSTA - Performs static timing analysis on the resulting netlist to generate timing reports Floorplan and PDN init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing) ioplacer - Places the macro input and output ports pdn - Generates the power distribution network tapcell - Inserts welltap and decap cells in the floorplan Placement RePLace - Performs global placement Resizer - Performs optional optimizations on the design OpenDP - Perfroms detailed placement to legalize the globally placed components CTS TritonCTS - Synthesizes the clock distribution network (the clock tree) Routing FastRoute - Performs global routing to generate a guide file for the detailed router CU-GR - Another option for performing global routing. TritonRoute - Performs detailed routing SPEF-Extractor - Performs SPEF extraction GDSII Generation Magic - Streams out the final GDSII layout file from the routed def Klayout - Streams out the final GDSII layout file from the routed def as a back-up Checks Magic - Performs DRC Checks & Antenna Checks Klayout - Performs DRC Checks Netgen - Performs LVS Checks CVC - Performs Circuit Validity Checks OpenLANE Files The openLANE file structure looks something like this: skywater-pdk: contains PDK files provided by foundry open_pdks: contains scripts to setup pdks for opensource tools sky130A: contains sky130 pdk files Invoking OpenLANE and Design Preparation Openlane can be invoked using docker command followed by opening an interactive session. flow.tcl is a script that specifies details for openLANE flow. Tools used for physical Design Python Installation $ sudo apt install -y build-essential python3 python3-venv python3-pip Docker Installation $ sudo apt-get remove docker docker-engine docker.io containerd runc (removes older version of docker if installed) $ sudo apt-get update $ sudo apt-get install \ ca-certificates \ curl \ gnupg \ lsb-release $ sudo mkdir -p /etc/apt/keyrings $ curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo gpg --dearmor -o /etc/apt/keyrings/docker.gpg $ echo \ "deb [arch=$(dpkg --print-architecture) signed-by=/etc/apt/keyrings/docker.gpg] https://download.docker.com/linux/ubuntu \ $(lsb_release -cs) stable" | sudo tee /etc/apt/sources.list.d/docker.list > /dev/null $ sudo apt-get update $ sudo apt-get install docker-ce docker-ce-cli containerd.io docker-compose-plugin $ apt-cache madison docker-ce (copy the version string you want to install) $ sudo apt-get install docker-ce=<VERSION_STRING> docker-ce-cli=<VERSION_STRING> containerd.io docker-compose-plugin (paste the version string copies in place of <VERSION_STRING>) $ sudo docker run hello-world (If the docker is successfully installed u will get a success message here) OpenLane Installation $ git clone https://github.com/The-OpenROAD-Project/OpenLane.git $ cd OpenLane/ $ make $ make test Magic Installation For Magic to be installed and work properly the following softwares have to be installed first: Installing csh $ sudo apt-get install csh Installing x11/xorg $ sudo apt-get install xorg $ sudo apt-get install xorg openbox Installing GCC $ sudo apt-get install gcc Installing build-essential $ sudo apt-get install build-essential Installing OpenGL $ sudo apt-get install freeglut3-dev Installing tcl/tk $ sudo apt-get install tcl-dev tk-dev Installing magic After all the softwares are installed, run the following commands for installing magic: $ cd magic $ ./configure $ make $ make install Klayout Installation $ sudo apt-get install klayout ngspice Installation $ sudo apt-get install ngspice Creating a Custom Inverter Cell Open Terminal in the folder you want to create the custom inverter cell. $ git clone https://github.com/nickson-jose/vsdstdcelldesign.git $ cd vsdstdcelldesign $ cp ./libs/sky130A.tech sky130A.tech $ magic -T sky130A.tech sky130_inv.mag & image The above layout will open. The design can be verified and various layers can be seen and examined by selecting the area of examination and type what in the tcl window. To extract Spice netlist, Type the following commands in tcl window. % extract all % ext2spice cthresh 0 rthresh 0 % ext2spice cthresh 0 rthresh 0 is used to extract parasitic capacitances from the cell. image The spice netlist has to be edited to add the libraries we are using, The final spice netlist should look like the following: * SPICE3 file created from sky130_inv.ext - technology: sky130A 342 ​ 343 .option scale=10000u 344 ​ 345 .subckt sky130_inv A Y VPWR VGND 346 M1000 Y A VPWR VPWR pshort w=37 l=23 347 + ad=1443 pd=152 as=1517 ps=156 348 M1001 Y A VGND VGND nshort w=35 l=23 349 + ad=1435 pd=152 as=1365 ps=148 350 C0 VPWR A 0.07fF 351 C1 VPWR Y 0.11fF 352 C2 Y A 0.05fF 353 C3 Y VGND 0.24fF 354 C4 VPWR VGND 0.59fF 355 .ends Open the terminal in the directory where ngspice is stored and type the following command, ngspice console will open: $ ngspice sky130_inv.spice Now you can plot the graphs for the designed inverter model. -> plot y vs time a Four timing parameters are used to characterize the inverter standard cell: Rise time: Time taken for the output to rise from 20% of max value to 80% of max value Rise time = (2.23843 - 2.17935) = 59.08ps Fall time- Time taken for the output to fall from 80% of max value to 20% of max value Fall time = (4.09291 - 4.05004) = 42.87ps Cell rise delay = time(50% output rise) - time(50% input fall) Cell rise delay = (2.20636 - 2.15) = 56.36ps Cell fall delay = time(50% output fall) - time(50% input rise) Cell fall delay = (4.07479 - 4.05) = 24.79ps To get a grid and to ensure the ports are placed correctly we can use % grid 0.46um 0.34um 0.23um 0.17um image Layout Preparation The layout is generated using OpenLane. To run a custom design on openlane, Navigate to the openlane folder and run the following commands: $ cd designs $ mkdir iiitb_alu $ cd iiitb_alu $ mkdir src $ touch config.json $ cd src $ touch iiitb_alu.v The iiitb_alu.v file should contain the verilog RTL code you have used and got the post synthesis simulation for. Copy sky130_fd_sc_hd__fast.lib, sky130_fd_sc_hd__slow.lib, sky130_fd_sc_hd__typical.lib and sky130_vsdinv.lef files to src folder in your design. The final src folder should look like this: image The contents of the config.json are as follows. this can be modified specifically for your design as and when required. { "DESIGN_NAME": "iiitb_alu", "VERILOG_FILES": "dir::src/iiitb_alu.v", "CLOCK_PORT": "clk", "CLOCK_NET": "clk", "GLB_RESIZER_TIMING_OPTIMIZATIONS": true, "CLOCK_PERIOD": 10, "PL_TARGET_DENSITY": 0.7, "FP_SIZING" : "relative", "pdk::sky130*": { "FP_CORE_UTIL": 30, "scl::sky130_fd_sc_hd": { "FP_CORE_UTIL": 20 } }, "LIB_SYNTH": "dir::src/sky130_fd_sc_hd__typical.lib", "LIB_FASTEST": "dir::src/sky130_fd_sc_hd__fast.lib", "LIB_SLOWEST": "dir::src/sky130_fd_sc_hd__slow.lib", "LIB_TYPICAL": "dir::src/sky130_fd_sc_hd__typical.lib", "TEST_EXTERNAL_GLOB": "dir::../iiitb_alu/src/*" } Save all the changes made above and Navigate to the openlane folder in terminal and give the following command : $ sudo make mount image After entering the openlane container give the following command: $ ./flow.tcl -interactive image This command will take you into the tcl console. In the tcl console type the following commands: % package require openlane 0.9 image prep -design iiitb_alu image The following commands are to merge external the lef files to the merged.nom.lef. In our case sky130_vsdiat is getting merged to the lef file set lefs [glob $::env(DESIGN_DIR)/src/*.lef] add_lefs -src $lefs Synthesis % run_synthesis image Synthesis Reports Details of the gates used image Flop Ratio = Ratio of total number of flip flops / Total number of cells present in the design = 8/145 = 0.05517 The sky130_vsdinv should also reflect in your netlist after synthesis image Floorplan % run_floorplan image Floorplan Reports Die Area image Core Area image Navigate to results->floorplan and type the Magic command in terminal to open the floorplan $ magic -T /home/aashish/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read lef ../../tmp/merged.nom.lef def read iiitb_alu.def & floorplan Floorplan view image All the cells are placed in the left corner of the floorplan image Placement run_placement image Placement Reports Navigate to results->placement and type the Magic command in terminal to open the placement view $ magic -T /home/aashish/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read lef ../../tmp/merged.nom.lef def read iiitb_alu.def & placement Placement View image image sky130_vsdinv in the placement view : pl_inv The sky130_vsdinv should also reflect in your netlist after placement image Clock Tree Synthesis % run_cts image Routing % run_routing image Routing Reports Navigate to results->routing and type the Magic command in terminal to open the routing view $ magic -T /home/aashish/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read lef ../../tmp/merged.nom.lef def read iiitb_alu.def & routing Routing View image sky130_vsdinv in the routing view : rt_inv The sky130_vsdinv should reflect in your netlist after routing image We can also run the whole flow at once instead of step by step process by giving the following command in openlane container $ ./flow.tcl -design iiitb_alu autoflow All the steps will be automated and all the files will be generated. image Viewing Layout in KLayout Navigate to results->signoff and type the Magic command in terminal to open the routing view $ klayout iiitb_alu.mag image Analysis Summary Post-synthesis Gate count of the design (stat) Gate Count = 145 stats No. of flip-flops = 8 No. of standard cells = 145 Flip-flop to standard cell ratio =0.055 Area of the design Area = 9663.672 um^2 area Performance (report_checks) GHz/MHz achieved for the design Performance = (1/(Clock Period - Slack)) Performance of design = 1/(10-6.5) = 2.85714 GHz performance Power consumed for the design Total Power = 1.73e-04 watts report_power Design Folder iiitb_alu ├── config.jason ├── runs │ ├── RUN_2022.09.01_11.03.54 │ │ ├── config.tcl │ │ ├── logs │ │ │ ├── cts │ │ │ ├── cvc │ │ │ ├── floorplan │ │ │ ├── klayout │ │ │ ├── magic │ │ │ ├── placement │ │ │ ├── routing │ │ │ └── synthesis │ │ ├── reports │ │ │ ├── cts │ │ │ ├── cvc │ │ │ ├── floorplan │ │ │ ├── klayout │ │ │ ├── magic │ │ │ ├── placement │ │ │ ├── routing │ │ │ └── synthesis │ │ ├── results │ │ │ ├── cts │ │ │ ├── cvc │ │ │ ├── floorplan │ │ │ ├── klayout | | | ├── signoff │ │ │ ├── magic │ │ │ ├── placement │ │ │ ├── routing │ │ │ └── synthesis │ │ └── tmp │ │ ├── cts │ │ ├── cvc │ │ ├── floorplan │ │ ├── klayout │ │ ├── magic │ │ ├── placement │ │ ├── routing │ │ └── synthesis ├── src ├── iiitb_alu.v ├── sky130_fd_sc_hd__fast.lib ├── sky130_fd_sc_hd__slow.lib ├── sky130_fd_sc_hd__typical.lib ├── sky130_vsdinv.lef Contributors Aashish Tiwary Kunal Ghosh Acknowledgments Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. Contact Information Aashish Tiwary, Postgraduate Student, International Institute of Information Technology, Bangalore aashish.tiwary@iiitb.ac.in Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. kunalghosh@gmail.com