Efabless Repositories
Code hosting system for your Efabless projects
All Projects 573
vilmondesribeiro / 9-stages-ring-oscilator
This is a ring oscilator made with 9 stages of CMOS inverters.
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Updated 11 months ago
manikandan_nagarajan / Caravel_Multi_encoder
Multi purpose integrated encoder
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Updated 2 years ago
abdullahyildiz / YONGA-LZ4-Decoder
YONGA-LZ4 Decoder Is An Implementation Of The Decoder Of The Popular Lz4 Compression Algorithm.
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Updated a month ago
amrotork / Digital-PLL
Integer Digitall PLL + LDO + Bandgap + Error Amplifier Design
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Updated 2 months ago
andreoulab_chips / Telluride-Neuromorphic-Acoustic-Front-End
An auditory perception acoustic front end with multi-channel capability and standard digital interfaces (I2S, PDM and SPI). This project was conceived and developed by participants of the the 2021 NSF Telluride Neuromorphic Cognition Engineering Workshop (June 28 - July 19, 2021).
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Updated 7 months ago
hishamelreedy / Bandgap-Reference
Design of bandgap reference circuit which can be used as building block for power management ICs
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Updated a year ago
michaelstetzler / RF_IQ_Upconverter_Downconverter_Device
Upconverter/Downconverter with integrated with image rejection, RF gain stage, and LO chain that includes frequency multiplier, tunable BP filter, I/Q phase control, and VGA.
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Updated 3 years ago
tim_edwards / Chaos-Automaton
Asynchronous automaton with evolvable edge-of-chaos behavior
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Updated a year ago
jeetsumanto123 / Sziklai-Pair-Amplifier
This project focuses on design of a Sziklai Pair Amplifier using Google Skywater (sky130) Technology node with operating voltage of 1.8V and 3.3V.
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Updated a year ago
rohinthram / Two-Stage-CMOS-Operational-Amplifier
Two Stage CMOS Operational Amplifier
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Updated a year ago
abdullahyildiz / YONGA-100M-Ethernet
YONGA-100M Ethernet is based on the implementation of Alex Forencich's 100Mbps Ethernet design.
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Updated a month ago
amrotork / 1V8-LDO-Design-in-Skywaters-130nm
1V8 LDO Design in Skywaters 130nm
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Updated 2 months ago
skandhadeepsita / Approximate-Multiplier
This project is implementation of approximate multiplier published in ACM TODAES journal 2021, titled "Energy Efficient Error Resilient Multiplier Using Low-power Compressors".
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Updated 7 months ago
rohinthram / Two-Stage-CMOS-OPAMP
This project presents the design of a two stage CMOS Operational Amplifier. This ciruit provides a very good slew rate.
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Updated a year ago
adithyasunil26 / Microwave-Signal-Generator
2.87 GHz microwave signal generator with a small programmable sweep step size.
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Updated 4 months ago
ryanwans / Baseband-Inductorless-Automatic-Gain-Control
An Automatic Gain Control (AGC) feedback-loop oriented towards baseband applications (0-600 MHz) without the need for integrated inductors.
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Updated a year ago
derekcom17 / DDR3-SSTL-Test
Test chip for a DDR3 SSTL driver.
This chip will evaluate the performance of this this circuit, and test emulation of the DDR3 calibration process.
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Updated 8 months ago
simon_waid / TIA-for-physic-experiments
This project implements a low-noise high bandwidth (~1GHz) transimpedance amplifier (TIA). The TIA is complemented by a reference current generator and a 50 Ohm output driver
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Updated 10 months ago
dineshannayya / LBIST-MBIST
Logic BIST with Scan Chain to detect struck at fault
MBIST with 4 Location Row Redundancy Support
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Updated 2 years ago
vsdevaraddi / Systolic_array
We design a 2-D systolic array architecture as shown in teh figure. Each node is a Processing ELement (PE) which takes in 3 inputs and produces an output. Each PE shifts the data of horizontally and vertically to the neighboring PEs every clock cycle. Systolic arrays access the memory only once, and all the PEs transfer the data to the nearby...
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Updated 2 years ago
onurkrts / RNG-CHAOS
In this study, a digital RNG based on chaotic oscillators was implemented using the SKY130 process node.
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Updated 11 months ago
ac3e_chile_chipathon_team / DC-DC-Buck-Converter-for-efficient-CubeSat-EPS
This project aims to design and implement a DC-DC buck converter based on the Three-level Flying Capacitor Converter (3L-FCC) architecture for space applications, namely CubeSat systems, using the Skywater 130nm CMOS technology. In our proposal, the power circuits are fully integrated on-chip, including the power MOSFETs (PM), the flying...
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Updated a year ago
amrtawfik / CMOS-Power-Oscillator-Test-Chip
A CMOS 915 MHz power oscillator test chip consists of a driving cross coupled LC oscillator followed by a differential power amplifier is designed to compare the performance of three classes of power amplifiers (C, E and F). The key performance metrics are efficiency and output power level. The target application is far field wireless charging...
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Updated 6 months ago
asgaris / Mixed-Signal-SoC-for-Nanopore-Based-DNA-Sequencing
Nanopore-based DNA sequencing is a unique, scalable technology, utilized to identify nucleotides (i.e., A, C, G, T) according to the pico-ampere-sized current fluctuations induced by the passage of a DNA strand through a nanopore. The main components of this technology fit in the palm of one’s hand and it has demonstrated the ability to process...
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Updated 8 months ago
anizam / Electrochemical-Water-Quality-Monitoring
The goal of this project is to design and fabricate a low power low cost electrochemical sensing system to monitor the quality of water. A three-electrode electrochemical sensor will perform amperometry and cyclic voltammetry and send the captured voltage signal into the analog front end module. The analog signal is amplified, digitized, and...
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Updated a year ago
merldsu2 / Floating_Point_Unit_Single_Precision
This is the first ever Single Precision Floating Point Unit designed by Undergraduate Students of DHA Suffa Univeristy
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Updated 2 years ago
merldsu2 / Floating_Point_Unit_Bfloat16
This is the first ever Bfloat16 precision floating point unit designed by undergraduate students of DHA Suffa University Pakistan
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Updated 2 years ago
wevel / Experiar-SoC
Experiar SoC is a dual RV32I core processor with peripherals including PWM, SPI, UART, and VGA.
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Updated a year ago
danielsantos7 / Leaf
a small 32-bit RISC-V core for IoT applications.
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Updated 2 years ago
ria183422005 / Optimised-Strong-ARM-Latch
This is the design of an optimised Strong ARM Latch using modified particle swarm optimisation.
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Updated 9 months ago
janjayaraman / Four-Bit-ALU_XOR---MPW-6
This is a digital 4-bit ALU_XOR design.
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Updated a year ago
nix / TopmetalSe-A-Low-Noise-Pixelated-Charge-Sensor
The TopmetalSe is a pixelated charge sensor in the Skywater 130nm process, designed for the Selena Neutrino experiment as an imager for rare nuclear processes in amorphous Selenium.
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Updated 6 months ago
nix / TopmetalSe-A-Pixelated-Charge-Sensor
The TopmetalSe is a pixelated charge sensor in the Skywater 130nm process, designed for the Selena Neutrino experiment as an imager for rare nuclear processes in amorphous Selenium.
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Updated 12 months ago
nguyendao / RocketAlpha
This project demonstrates a customized Rocket Chip SoC, generated from Chipyard. The SoC is implemented in Sky130nm using the Openlane flow
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Updated a year ago
carllb / Mixed_signal_circuits-Jun13
We have a 2x2 1T1R ReRam structure and a C4 Filter as well as some other supporting analog circuits for mixed-signal computing.
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Updated a year ago
fatih_gulakar / Shooting-game
A simple shooting game in Verilog.
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Updated 11 months ago
s3jain / ReRAM_crossbar
ReRAM 16x16 array characterisation, including forming, incremental set and reset, and parallel analog read for vector-matrix multiplication. All characterisation is fully digitally controlled over the logic analyser.
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Updated a year ago
asgaris / Mixed-Signal-SoC-for-Nanopore-Based-DNA-Sequencing-2
Nanopore-based DNA sequencing is a unique, scalable technology, utilized to identify nucleotides (i.e., A, C, G, T) according to the pico-ampere-sized current fluctuations induced by the passage of a DNA strand through a like-sized molecular sensor (i.e. a “nanopore”). This approach, a so-called “3rd Generation” sequencing technology, entered...
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Updated 8 months ago
danielsantos7 / Leaf-(mpw7)
Leaf is a small 32-bit RISC core for simple applications.
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Updated 9 months ago
shumpeikawasaki / Marmot-RISC-V-ASIC-large-memory-and-Motor-Control
Increased features (plus 8KB D-Cache and 3ch PWM）and improved clocking (25MHz > 50MHz) by mastering tools since MPW-6 MARMOT RISC-V, three months ago.
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Updated a month ago
nix / TopmetalSe-DPS
The TopmetalSe is a pixelated charge sensor in the Skywater 130nm process, designed for the Selena Neutrino experiment as an imager for rare nuclear processes in amorphous Selenium.
The TopmetalSe-DPS is a prototype/upgrade of the TopmetalSe that was previously submitted for tapeout. We include a "digital pixel sensor," where we digitize the...
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Updated a year ago
cmantas / Bitcoin-Mining-Asic
This ASIC takes as an input the header of a Blockchain and simulates the bitcoin mining process.
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Updated 9 months ago
abdullahyildiz / YONGA-CAN-Controller
YONGA-CAN Controller is a partial implementation of CAN 2.0B standard.
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Updated a month ago
burak_aykenar / YONGA-MCU
Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C.
The design is based on famous pulp team's pulpino. We (Yongatek Microelectronics from Turkiye) try to tape-out this MCU to gain experience on openlane flow with MPW7 with minor modifications from the original pulpino work. You can...
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Updated a year ago
