Efabless Repositories
Code hosting system for your Efabless projects
All Projects 573
karthikmb / ai_solar_panel_monitor
Stabilising the current, voltage of the solar panel under controlled temerature
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Apache-2.0
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Updated a year ago
cal_poly_carp / CARP_SOC_2023
Cal Poly Computer Architecture Research Project (CARP)'s SoC, SRAM, and Peripherals, set up to measure reliability in a radioactive environment.
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Apache-2.0
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Updated a year ago
emilgoh / ThreePhase_PWM_Generator
With the increasing demand for renewable energy and automation with drones and robots, the three-phase PWM technique is an essential component in a chip to drive motors and manage power in power electronic systems, facilitating a smooth conversion of electrical energy.The design also included dead time, which is essential in preventing short...
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Apache-2.0
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Updated a year ago
baungarten / HW_TI_Encryption
AI Hardware Attack Challenge, CINVESTAV-DD team.
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Apache-2.0
tholin / tholin_multi_project
Multiple projects from multiple participants all on one die! Selected design gets access to the IO ports.
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Apache-2.0
ruigelee / Rift2Go_2300_GF180_MPW1
Rift2300 Resubmission
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Apache-2.0
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Updated a year ago
duyhieubui / UNIC-CASS-IC4
This is the merged designs of IC4 in UNIC-CASS Program.
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Apache-2.0
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Updated a year ago
delini1612 / EDABK_Brain_SoC
A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.
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Apache-2.0
zanjani / GTO1
Analog and mixed signal project including SAR ADC
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Updated a year ago
noritsuna / micro_irritating_maze
This is a maze game played with tools using semiconductor chips before bonding. Specifically, the game is to use a 5um Tungsten Needle while looking into a semiconductor chip with a stereo microscope to go through a maze drawn with pads on the semiconductor chip.At this time, when the needle touches the maze wall, the LED for the crash judgment...
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Apache-2.0
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Updated 11 months ago
mole99 / LeoSoC-GFMPW-1
A simple dual-core SoC with a range of true random number generators as payload.
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Updated a year ago
thomas717 / DFF-based_PUF
An array designed to evaluate the stability and reliability over various physical environment of DFF-based PUF using ML-assisted method to create initialization data. The chip is designed to evaluate the GF180MCU node for PUF design and help the development of the debiasing scheme. PUF-based key generation should further enhance the security of...
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Apache-2.0
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Updated a year ago
bslathi19 / quite_okay_accelerator
A pipelined QOI encode/decode accelerator designed.
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Apache-2.0
zanjani / GTO2
Analog and mixed signal project including SAR ADC
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Updated a year ago
zanjani / GTO3
Analog and mixed signal project including SAR ADC
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Updated a year ago
hl271 / edabk_brain_soc_w_synthesis
A project dedicated to developing a hardware-software co-design for neurosynaptic core based on Spike Neural Network (SNN) architecture, integrated with RISC-V based SoC, powered by the RTL code generated by ChatGPT-4 with advanced optimizations.
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Updated a year ago
piotro888 / ppcpu-3
Pipelined microprocessor with custom RISC architecture! (with caches and exported full system bus)
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Apache-2.0
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Updated a year ago
ganga / CLIPSAFE
efabless chipIgnite incorporated project
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Apache-2.0
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Updated a year ago
potereau / Chirper
First version of a chirp generator with complementary (sin and cos) output
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Updated a year ago
anandriisc / Design_VCO_for_RF
Design of low noise voltage controlled oscillator using 130 nm library meeting low power better performance and in minimum silicon area. This can be used as an application in RF communication engineering in transceivers in mobile handsets.
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Updated a year ago
ishikai / ISHI-KAI_Multiple_Projects_OpenGFMPW-1
This project is a compilation of ISHI-KAI members' individual analog circuit projects for OpenGFMPW-1.
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Updated a year ago
willa / Research_JHHS
Dynamic CGRA-based accelerator prototype for RISC-V.
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Updated a year ago
urielcho / ITA23_GFMPW1
The primary objective of this project was to impart knowledge about the fundamentals of microchip creation using 130nm and 180nm technology. Key concepts, from Verilog design to obtaining the final GDS layout for fabrication, were covered.
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Apache-2.0
moacir_monteiro / myFirstProject
First project to have a better compreension of the flow
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Updated a year ago
urish / tinytapeout-06
Tiny Tapeout 06 - Visit https://tinytapeout.com for more information on the project and how to get involved
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Updated 7 months ago
rohinthram / ArithmeticLogicUnit
An ALU design that can do arithmetic and logical computation that can be used to build a CPU
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Updated a year ago
mvsegal08 / Spiking_Neuron_Cluster
Asynchronous digital neuromorphic network build from leaky integrate and fire neurons. In the works!
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afasolino28 / DAA
An accumulation algorithm to adapt multiplier results to fixed width of the adder
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navan93 / RiscV_SoC
This is a RiscV SoC based on the OpenHW group's CV32E40P CPU.
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Apache-2.0
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Updated a year ago