Cal Poly CARP SOC

Checklist for Open-MPW Submission

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• <input type="checkbox" checked="" disabled=""> The project repo adheres to the same directory structure in this repo.
• <input type="checkbox" checked="" disabled=""> The project repo contain info.yaml at the project root.
• <input type="checkbox" checked="" disabled=""> Top level macro is named user_project_wrapper.
• <input type="checkbox" disabled=""> Full Chip Simulation passes for RTL and GL (gate-level)
• <input type="checkbox" checked="" disabled=""> The hardened Macros are LVS and DRC clean
• <input type="checkbox" checked="" disabled=""> The project contains a gate-level netlist for user_project_wrapper at verilog/gl/user_project_wrapper.v
• <input type="checkbox" checked="" disabled=""> The hardened user_project_wrapper adheres to the same pin order specified at pin\_order <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/pin_order.cfg>__
• <input type="checkbox" checked="" disabled=""> The hardened user_project_wrapper adheres to the fixed wrapper configuration specified at fixed_wrapper_cfgs <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl>__
• <input type="checkbox" checked="" disabled=""> XOR check passes with zero total difference.
• <input type="checkbox" checked="" disabled=""> Openlane summary reports are retained under ./signoff/
• <input type="checkbox" checked="" disabled=""> The design passes the mpw-precheck <https://github.com/efabless/mpw_precheck>__