Files
Portland State University WEST Lab GFMPW-1 Submission
| :exclamation: Important Note |
|---|
This is the repository for the WEST Lab*'s Submission for GFMPW-1.
*WEST Lab, Department of Electrical and Computer Engineering, Portland State University.
Below is a list of projects included in our implementation for this submission:
- SCuM I/Q ADC Decoder for BLE Modulation using Matched Filter (Jacob Louie)
- BLE Packet Decoder/Sniffer (Brandon Hippe)
- Various Oscillator stability test circuits (Haziq Rohail)
1. Matched Filter
| GPIO # | Name | Input/Output |
|---|---|---|
| 5 | Clock | Input |
| 7:6 | Select | Input |
| 8 | Reset | Input |
| 9 | Update | Input |
| 13:10 | I_BPF | Input |
| 21:14 | MF_Output | Output |
| 22 | Data | Output |
Description
Clock: The expected input clock frequency is 16MHz. Not recomended to go over 20 MHz.
Select: The 2 select pins are used to switch between the differnt wireless comunication standards. GPIO pin 7 is the MSB and pin 6 is the LSB. The Low MHz frequency for each template represents 0 for the data bit and the high MHz frequency represents 1 for the data bit (could also be reversed).
| Input (Value) | Mode | Template |
|---|---|---|
| 0 | Bluetooth | 1MHz-2MHz |
| 1 | 802.15.4 | 2MHz-3MHz |
| 2 | Bluetooth | 1.5MHZ-2MHz |
| 3 | Bluetooth | 1MHz-1.5MHz |
Reset: The reset pin as active high. This pin will clear the I_BPF buffer and clear the value held on the data bit.
Update: This pin is used to update the data bit. A clock sycronized with the data coming in on the I_BPF pins is what's expected on this input. For 802.15.4 with a 16MHz sample rate on I_BPF, the update pin clock rate would be 1MHz. For Bluetooth LE with a sample rate of 16MHz, the update pin clock rate would be 0.5MHz.
I_BPF: The I_BPF (I_Band Pass Filter) can be eithert the I_BPF or the Q_BPF signal. The I_BPF is a 4 bit ADC value from 0-15 that repesents the frequency modulation of data being recieved.
MF_Output: The match filter output (MF_Output) pins are the sudo score for the low MHz and high MHz signals being recieved by the I_BPF. If the low MHz bits have a higher score than the signal being recived is a lower frequency signal, meaning the data output is a 0. If the high MHz bits have a higher score than the signal being recieved is a higher frequency signal, meaning the data output a 1.
| GPIO [21:14] / Bits[7:0] | High/Low frequency |
|---|---|
| [21:18] / [7:4] | High Frequency Score |
| [17:14] / [3:0] | Low Frequency Score |
Data: This is the decoded 1 bit data.
2. BLE Packet Decoder/Sniffer
The BLE Packet Decoder/Sniffer module is designed to take in a 1MBit/s datastream and give an output whenever a valid BLE advertising packet is detected. This revision takes into account the Preamble, Access Address, and passing CRC check within the maximum packet length and at a byte line, and does not currently decode any of the data within the packet.
The module is configurable to input/output from either the GPIO, Logic Analyzer, or Wishbone Bus. The tables below list the necessary definitions for these signals.
Below is the block diagram for the BLE Packet Decoder/Sniffer
Control Register Definitions
There are 8 control registers, addressed by an 8 bit register address reg_addr. The register addresses for these registers are listed below.
| Control Register | Address(es) |
|---|---|
| Data | 0x00 |
| I/O Config | 0x01 |
| Channel | 0x02 |
| Access Address | 0x07:0x03 |
Data: This register provides data to the packet decoder. Only the least significant bit is supplied, therefore the contents of the most significant 7 bits do not matter.
I/O Config: This register configures the Input and Outputs to use the GPIO, Logic Analyzer, or Wishbone Bus. Each is configurable independently. Bits 3:2 configure the output, while bits 1:0 configure the input. For these values, supplying 0b00 selects the GPIO, 0b01 selects the logic analyzer, and 0b10 selects the wishbone bus.
Channel: This register supplies the channel to reset the dewhitening LFSR to. Only the channel number in 6-bit unsigned binary needs to be supplied, as the 7th always on bit for the LFSR initialization is handled by the dewhitening LFSR. This allows for the decoder to dewhiten packets on any of the 40 BLE channels (Default is channel 37).
Access Address: This register supplies the Access Address to match after the preamble of the packet. This is a 5-byte register. The MSB (0x07) is the preamble (0x55 or 0xAA) which is correct for the acccess address. The next 4 bytes (0x06:0x03) are the access address, MSB to LSB (it is important to note that the Access Address is transmitted least significant bit first, so this value is reversed to transmission order). This allows for the decoder to match any access address supplied (Default is 0x558E89BED6, the preamble and access address for advertising packets).
GPIO
| GPIO # | Name | Input/Output | Reference Value (below) |
|---|---|---|---|
| 30:23 | gpio_data | Input | data |
| 33:31 | gpio_reg_addr | Input | reg_addr |
| 34 | gpio_clock | Input | clock |
| 35 | gpio_reset | Input | reset |
| 36 | packet | Output | packet |
Logic Analyzer
| LA # | Name | Input/Output | Reference Value (below) |
|---|---|---|---|
| 7:0 | la_data_in | Input | data |
| 15:8 | la_regAddr_in | Input | reg_addr |
| 16 | la_clk | Input | clock |
| 17 | la_reset | Input | reset |
| 18 | packet | Output | packet |
Wishbone Bus
| WB Addr/Signal | Name | Input/Output | Reference Value (below) |
|---|---|---|---|
| i_wb_data[7:0] | wb_data | Input | data |
| i_wb_data[15:8] | wb_reg_addr | Input | reg_addr |
| wb_clk_i | wb_clock | Input | clock |
| wb_rst_i | wb_reset | Input | reset |
| o_wb_data[0] | packet | Output | packet |
The address for the BLE packet sniffer on the wishbone bus is 0x30000000.
data: Data to be written to device register currently pointed to by reg_addr.
reg_addr: Address to write to reg_addr on next clock cycle (Note: not the register address for *_data on this clock cycle, but the next).
clock: Clock signal for the BLE packet decoder.
reset: Reset signal for the BLE packet decoder.
packet: Packet found output from BLE decoder. Normally low, goes high two cycles after last data bit of a valid packet is supplied.
3. Analog Projects
The analog portion of the chip consists of three different oscillator topologies for characterizing the flicker noise of the gf180 process, an operational amplifier, an LC Tank, and large NMOS transistors for various etching projects. The block includes seven GSG pads for RF measurements, and nine single ended pads for various VDD and control signals. A brief description of the projects is given here.
Ring Oscillator circuit
The ring oscillator is made by connecting three inverters in a chain, and a large driver at the output. The 6V transistors with sizes of 1um/0.7um for NMOS and 2um/0.7um for PMOS are used. The driver is an inverter with 20 4um fingers for NMOS and 20 8um fingers for PMOS.
Differential Ring Oscillator circuit
The differential ring oscillator is made using five differential delay cells, wherein each delay cell consists of an NMOS differential pair, a PMOS cross coupled pair and an NMOS base transistor for controlling the circuit’s frequency.
A current starved Ring Oscillator circuit
The current starved ring oscillator is a slightly modified version of the ring oscillator with an input signal to adjust its frequency.
60um x 60um NMOS Transistors
Multiple large 60um x 60um NMOS transistors are made for etching projects. The metal stack on top of one transistor will be etched through to expose the polysilicon gate underneath for measurements to evaulate the validity of post-fabrication etching for new sensor technologies.
Two Stage Operational Amplifier
A two stage operational amplifier circuit is designed for high frequency applications.
LC Tank
An LC Tank is included, and will be used to improve our ability for characterizing LC Tank circuits for use as on-chip oscillators.