Riscduino Dual Risc Core SOC


Permission to use, copy, modify, and/or distribute this soc for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.

THE SOC IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOC INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOC.

Table of contents

Overview

Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arduino platform and this soc targeted for efabless Shuttle program. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.

Riscduino Block Diagram

Key features

    * Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
    * Dual 32 Bit RISC-V core
    * 2KB SRAM for instruction cache 
    * 2KB SRAM for data cache
    * 2KB SRAM for Tightly coupled memory - For Data Memory
    * Quad SPI Master with 4 Chip select, supports both SPI flash and SRAM interface
    * 2 x UART with 16Byte FIFO
    * USB 1.1 Host
    * I2C Master
    * UART Master
    * Simple SPI Master with 4 Chip select
    * 6 Channel ADC (in Progress)
    * 6 x PWM
    * 3 x Timer (16 Bit), 1us/1ms/1second resolution
    * 2 x ws281x driver
    * 16 Hardware Semaphore
    * FPU (SP) Core
    * AES 128 Bit Core
    * RTC Core
    * Pin Compatbible to arduino uno
    * Wishbone compatible design
    * Written in System Verilog
    * Open-source tool set
       * simulation - iverilog
       * synthesis  - yosys
       * backend/sta - openlane tool set
    * Verification suite provided.

Riscduino derivatives

MPW Shuttle on Riscduino

MPW Tape-out Project Name Project Details Github Efabless Tapeout Link
MPW-2 18-June-2021 YiFive Single 32bit RISCV core without cache + SDRAM Controller + WB Interconnect Link Link Link
MPW-3 15-Nov-2021 Riscduino Single 32bit RISCV core without cache + Onchip SRAM + WB Interconnect Link Link Link
MPW-4 31-Dec-2021 Riscduino-R1 Single 32bit RISCV core with cache + Onchip SRAM + WB Inter Connect Link Link Link
MPW-5 21-Mar-2022 Riscduino-DCORE (D0) Dual 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar Link Link Link
MPW-5 21-Mar-2022 Riscduino-QCORE (Q0) Quad 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar Link Link Link
MPW-6 07-June-2022 Riscduino-SCORE (S3) Single 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar Link Link Link
MPW-6 07-June-2022 Riscduino-DCORE (D1) Dual 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar Link Link Link
MPW-6 07-June-2022 Riscduino-QCORE (Q1) Quad 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar Link Link Link
MPW-7 12-Sept-2022 Riscduino-SCORE (S4) Single 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar Link Link Link
MPW-7 12-Sept-2022 Riscduino-DCORE (D3) Dual 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar Link Link Link
MPW-7 12-Sept-2022 Riscduino-QCORE (Q1) Quad 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar Link Link Link
MPW-8 31-Dec-2022 Riscduino-DCORE (D4) Dual 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar Link Link Link
MPW-8 12-Sept-2022 Riscduino-QCORE (Q3) Quad 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar Link Link Link

SOC Pin Mapping

Carvel SOC provides 38 GPIO pins for user functionality. Riscduino SOC GPIO Pin Mapping as follows vs ATMEGA328 and Arudino

ATMGA328 Pin No Functionality Arudino Pin Name Carvel Pin Mapping
Pin-1 PC6/RESET D20 digital_io[5]
Pin-2 PD0/RXD[0] D0 digital_io[6]
Pin-3 PD1/TXD[0] D1 digital_io[7]/analog_io[0]
Pin-4 PD2/RXD[1]/INT0 D2 digital_io[8]/analog_io[1]
Pin-5 PD3/INT1/OC2B(PWM0) D3 digital_io[9]/analog_io[2]
Pin-6 PD4/TXD[1] D4 digital_io[10]/analog_io[3]
Pin-7 VCC -
Pin-8 GND -
Pin-9 PB6/XTAL1/TOSC1 D21 digital_io[11]/analog_io[4]
Pin-10 PB7/XTAL2/TOSC2 D22 digital_io[12]/analog_io[5]
Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 D5 digital_io[13]/analog_io[6]
Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 D6 digital_io[14]/analog_io[7]
Pin-13 PD7/A1N1 D7 digital_io[15]/analog_io[8]
Pin-14 PB0/CLKO/ICP1 D8 digital_io[16]/analog_io[9]
Pin-15 PB1/SS[1]OC1A(PWM3) D9 digital_io[17]/analog_io[10]
Pin-16 PB2/SS[0]/OC1B(PWM4) D10 digital_io[18]/analog_io[11]
Pin-17 PB3/MOSI/OC2A(PWM5) D11 digital_io[19]/analog_io[12]
Pin-18 PB4/MISO D12 digital_io[20]/analog_io[13]
Pin-19 PB5/SCK D13 digital_io[21]/analog_io[14]
Pin-20 AVCC -
Pin-21 AREF analog_io[23]
Pin-22 GND -
Pin-23 PC0/uartm_rxd/ADC0 D14/A0 digital_io[22]/analog_io[15]
Pin-24 PC1/uartm/ADC1 D15/A1 digital_io[23]/analog_io[16]
Pin-25 PC2/usb_dp/ADC2 D16/A2 digital_io[24]/analog_io[17]
Pin-26 PC3/usb_dn/ADC3 D17/A3 digital_io[25]/analog_io[18]
Pin-27 PC4/ADC4/SDA D18/A4 digital_io[26]/analog_io[19]
Pin-28 PC5/ADC5/SCL D19/A5 digital_io[27]/analog_io[20]
Additional Pad used for Externam ROM/RAM/USB
Sflash sflash_sck digital_io[28]/Analog[21]
SFlash sflash_ss0 digital_io[29]/Analog[22]
SFlash sflash_ss1/AREF digital_io[30]/Analog[23]
SFlash sflash_ss2 digital_io[31]/Analog[24]
SFlash sflash_ss3 digital_io[32]/Analog[25]
SFlash sflash_io0 digital_io[33]/Analog[26]
SFlash sflash_io1 digital_io[34]/Analog[27]
SFlash sflash_io2 digital_io[35]/Analog[28]
SFlash sflash_io3 digital_io[36]
DEBUG dbg_clk_mon digital_io[37]
SPARE PA0 digital_io[0]
SPARE PA1 D23 digital_io[1]
SPARE PA2 D24 digital_io[2]
SPARE PA3 digital_io[3]
SPARE PA4 D25 digital_io[4]

Riscduino documentation

Arduino ide integration

Sub IP features

RISC V Core

Riscduino SOC Integrated Dual 32 Bits RISC V core. Initial version of Single core RISC-V core is picked from Syntacore SCR1 (https://github.com/syntacore/scr1)

RISC V core customization for Riscduino SOC

Following Design changes are done on the basic version of syntacore RISC core

   * Some of the sv syntex are changed to standard verilog format to make compatibile with opensource tool iverilog & yosys
   * local Instruction Memory depth increased from 4 to 8 location
   * Instruction Mem Request are changed from Single word to 4 Word Burst
   * Multiplication and Divsion are changed to improve timing
   * Additional pipe line stages added to improve the RISC timing closure near to 50Mhz
   * 2KB instruction cache 
   * 2KB data cache
   * Additional router are added towards instruction cache
   * Additional router are added towards data cache
   * Dual core related changes
   * Modified AXI/AHB interface to wishbone interface for instruction and data memory interface

Block Diagram

RISC V Core Key feature

   * RV32I or RV32E ISA base + optional RVM and RVC standard extensions
   * Machine privilege mode only
   * 2 to 5 stage pipeline
   * 2KB icache
   * 2KB dcache
   * Optional Integrated Programmable Interrupt Controller with 16 IRQ lines
   * Optional RISC-V Debug subsystem with JTAG interface
   * Optional on-chip Tightly-Coupled Memory

6 Channel SAR ADC

In Process - Looking for community help ...

SOC Memory Map

RISC IMEM RISC DMEM EXT MAP Target IP
0x0000_0000 to 0x0FFF_FFFF 0x0000_0000 to 0x0FFF_FFFF 0x0000_0000 to 0x0FFF_FFFF QSPI FLASH MEMORY
0x1000_0000 to 0x1000_00FF 0x1000_0000 to 0x1000_00FF 0x1000_0000 to 0x1000_00FF QSPI Config Reg
0x1001_0000 to 0x1001_003F 0x1001_0000 to 0x1001_003F 0x1001_0000 to 0x1001_003F UART
0x1001_0040 to 0x1001_007F 0x1001_0040 to 0x1001_007F 0x1001_0040 to 0x1001_007F I2C
0x1001_0080 to 0x1001_00BF 0x1001_0080 to 0x1001_00BF 0x1001_0080 to 0x1001_00BF USB
0x1001_00C0 to 0x1001_00FF 0x1001_00C0 to 0x1001_00FF 0x1001_00C0 to 0x1001_00FF SSPI
0x1001_01C0 to 0x1001_013F 0x1001_01C0 to 0x1001_013F 0x1001_01C0 to 0x1001_013F SSPI
0x1002_0080 to 0x1002_00FF 0x1002_0080 to 0x1002_00FF 0x1002_0080 to 0x1002_00FF PINMUX
- - 0x3080_0000 to 0x3080_00FF WB HOST

SOC Size

Block Total Cell Combo Seq
RISC 52527 46858 5669
QSPI 8654 7149 1505
UART_I2C_USB_SPI 15926 13061 2865
WB_HOST 5800 4701 1099
WB_INTC 11477 10081 1396
PINMUX 6746 5574 1172
TOTAL 120381 103826 16555

Prerequisites

  • Docker (ensure docker daemon is running) -- tested with version 19.03.12, but any recent version should suffice.

Step-1: Docker in ubuntu 20.04 version

   sudo apt update
   sudo apt-get install apt-transport-https curl rtificates -agent software-properties-common
   curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo apt-key add -
   sudo add-apt-repository "deb [arch=amd64] https://download.docker.com/linux/ubuntu focal stable"
   sudo apt update
   apt-cache policy docker-ce
   sudo apt install docker-ce

   #Add User Name to docker
   sudo usermod -aG docker <your user name>
   # Reboot the system to enable the docker setup

Step-2: Clone , update the Submodule, unzip the content

   git clone https://github.com/dineshannayya/riscduino.git
   cd riscduino
   git submodule init
   git submodule update
   make unzip

Note-1: RTL to GDS Docker

- Required openlane and pdk are moved inside the riscduino docker to avoid the external dependency. 
- flow automatically pull the required docker based on MPW version.
- RTL to gds docker is hardcoded inside File: openlane/Makefile
     OPENLANE_TAG = mpw9
     OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG)

Note-1.1: View the RTL to GDS Docker content

- for MPW-9 caravel pdk and openlane avaible inside riscduino/openlane:mpw9 docker 
- caravel, openlane and pdk envionment are automatically pointed to internal docker pointer
- To view the docker contents
    docker run -ti --rm riscduino/openlane:mpw9  bash
    cd /opt/pdk_mpw9     -  pdk folder
    cd /opt/caravel      -  caravel folder 
    cd /openlane         -  openlane folder
    env   - Show the internally defined env's
        CARAVEL_ROOT=/opt/caravel
        PDK_ROOT=/opt/pdk_mpw9

Note-2: RTL Simulation Docker

- Required caravel and pdk are moved inside the riscduino docker to avoid the external dependency. 
- flow automatically pull the required docker based on MPW version.
- To view the docker contents
- RTL simulation docker hardcoded inside File: Makefile
    simenv:
    docker pull riscduino/dv_setup:mpw6

Note-2.1: View the RTL Simulation Docker content

- for MPW-9 caravel and pdk avaible inside riscduino/dv_setup:mpw9 docker this is used for RTL to gds flows
- caravel and pdk envionment are automatically pointed to internal docker pointer
- To view the docker contents
    docker run -ti --rm riscduino/dv_setup:mpw9  bash
    cd /opt/pdk_mpw9     -  pdk folder
    cd /opt/caravel      -  caravel folder 
    env   - Show the internally defined env's
        CARAVEL_ROOT=/opt/caravel
        PDK_ROOT=/opt/pdk_mpw6

Note-3: Clock Gate Plugin integration

  1. Hack-1: Modify following files for synthesis script update
   Directory: OpenSTA (hacks/src/OpenSTA)
   Source Files:
       OpenLane/scripts/yosys/synth.tcl
       OpenLane/configuration/synthesis.tcl
       OpenLane/scripts/utils/utils.tcl
    Modifield File: 
       hacks/clk_gating/synth.tcl
       hacks/clk_gating/synthesis.tcl
       hacks/clk_gating/utils.tcl
  1. Hack-2: Create a pluging directory in openlane and add following files
plugin
   └── yosys
       └── Lighter
           ├── clock_gating_plugin.cc
           ├── README.md
           ├── sky130_clkg_blackbox.v
           └── sky130_ff_map.v
  1. Hack-3: Add ENV to enable clock gating in config.tcl
   set ::env(SYNTH_ENB_CG) 1
  1. Hack-4: Check Clock gate insertion in Generated netlist file
   grep sky130_fd_sc_hd__dlclkp  <your netlist file>

Tests preparation

The simulation package includes the following tests:

Standalone Riscduino SOC Specific Test case

  • 1.user_basic - Basic test case to validate strap and clocks
  • 2.user_uart - Standalone Risc with UART-0 Test
  • 3.user_uart1 - Standalone Risc with UART-1 Test
  • 4.user_risc_boot - Standalone User Risc core boot
  • 4.risc_boot - Complete caravel User Risc core boot
  • 5.user_qspi - Standalone Quad SPI test
  • 6.user_sspi - Standalone SSPI test
  • 7.user_i2c - Standalone I2C test
  • 8.user_usb - Standalone USB Host test
  • 9.user_gpio - Standalone GPIO Test
  • 10.user_aes - AES computation through Riscv core
  • 11.user_spi_isp - Device boot with SPI as ISP
  • 12.user_timer - Standalone timer Test
  • 13.user_uart_master - Standalone uart master test
  • 14.user_sram_exec - Riscv Boot with code running in SRAM
  • 15.user_cache_bypass - Riscv Boot without icache and dcache
  • 16.user_pwm -Standalone pwm Test
  • 17.user_sema -Standalone validation of hardware Semaphore function
  • 18.riscv_regress -Standalone riscv compliance and regression test suite
  • 19.user_rtc -Standalone RTC core test
  • 20.user_aes_core -Standalone AES Core test
  • 21.user_fpu_core -Standalone FPU(SP) Core test
  • 22.user_rtc -Standalone RTC core test
  • 24.user_ir_tx -Standalone IR Transmitted Test
  • 25.user_ir_rx -Standalone IR Receiver Test
  • 26.user_random - User Random core test
  • 27.step_motor_controller - Standalone Stepper Motor Controller

Caravel+RISCDUINO Integrated Specific Test case

  • 1.wb_port - Complete caravel User Wishbone validation
  • 2.uart_master_test1 - complete caravel user uart master test with baud control from LA port
  • 3.uart_master_test2 - complete caravel user uart master test based on auto baud detection
  • 4.risc_boot - Complete caravel User Risc core boot
  • 5.caravel_hkspi - Caravel House Keeping SPI test case

Arduino Based Test Case

  • 1.arduino_arrays - Validation of Array function
  • 2.arduino_digital_port_control - Validation for AD5206 digital potentiometer through SPI
  • 3.arduino_i2c_scaner - I2C port scanner
  • 4.arduino_risc_boot - Riscv Basic Boot
  • 5.arduino_timer_intr - Timer Interrupt handling
  • 6.arduino_ascii_table - Ascii Table Display
  • 7.arduino_gpio_intr - GPIO Interrupt generation
  • 8.arduino_i2c_wr_rd - I2C Write and Read access
  • 9.arduino_string - Validation of String function
  • 10.arduino_ws281x - Validation of ws281x serial protocol
  • 11.arduino_character_analysis - uart Input Character analysis
  • 12.arduino_hello_world - Basic hello world display
  • 13.arduino_multi_serial - Validation of Two Serail port
  • 14.arduino_switchCase2 - Validation of switch case

Running Simulation

Examples:

    make verify-wb_port                        - User Wishbone Test from caravel
    make verify-risc_boot                      - User Risc core test from caravel
    make verify-uart_master                    - User uart master test from caravel
    make verify-user_basic                     - Standalone Basic signal and clock divider test
    make verify-user_uart                      - Standalone user uart-0 test using user risc core
    make verify-user_uart1                     - Standalone user uart-0 test using user risc core
    make verify-user_i2cm                      - Standalone user i2c test
    make verify-user_risc_boot                 - standalone user risc core-0 boot test
    make verify-user_pwm                       - standalone user pwm test
    make verify-user_timer                     - standalone user timer test
    make verify-user_sspi                      - standalone user spi test
    make verify-user_qspi                      - standalone user quad spi test
    make verify-user_usb                       - standalone user usb host test
    make verify-user_gpio                      - standalone user gpio test
    make verify-user_aes                       - standalone aes test with risc core-0
    make verify-user_cache_bypass              - standalone icache and dcache bypass test with risc core-0
    make verify-user_uart_master               - standalone user uart master test
    make verify-user_sram_exec                 - standalone riscv core-0 test with executing code from data memory
    make verify-riscv_regress                  - standalone riscv compliance test suite
    make verify-arduino_risc_boot              - standalone riscv core-0 boot using arduino tool set
    make verify-arduino_hello_world            - standalone riscv core-0 hello world test using arduino tool set
    make verify-arduino_digital_port_control   - standalone riscv core-0 digital port control using arduino tool set
    make verify-arduino_ascii_table            - standalone riscv core-0 ascii table using arduino tool set
    make verify-arduino_character_analysis     - standalone riscv core-0 character analysis using arduino tool set
    make verify-arduino_multi_serial           - standalone riscv core-0 multi uart test using arduino tool set
    make verify-arduino_switchCase2            - standalone riscv core-0 switch case using arduino tool set
    make verify-arduino_risc_boot              - standalone riscv core-0 boot test using arduino tool set
    make verify-arduino_string                 - standalone riscv core-0 string usage test using arduino tool set

    make verify-user_mcore                     - standalone riscv multi-core test
    make verify-user_sram_exec RISC_CORE=1     - standalone riscv core-1 test with executing code from data memory
    make verify-user_risc_boot RISC_CORE=1     - standalone user risc core-1 boot test
    make verify-user_uart RISC_CORE=1          - Standalone user uart test using user risc core-1
    make verify-user_uart1 RISC_CORE=1         - Standalone user uart test using user risc core-1
    make verify-user_aes  RISC_CORE=1          - standalone aes test with risc core-1
    make verify-user_cache_bypass RISC_CORE=1  - standalone icache and dcache bypass test with risc core-1
    make verify-arduino_risc_boot RISC_CORE=1  - standalone riscv core-1 boot using arduino tool set

    make verify-user_uart SIM=RTL DUMP=OFF     - Standalone user uart-0 test using user risc core with waveform dump off
    make verify-user_uart SIM=RTL DUMP=ON      - Standalone user uart-0 test using user risc core with waveform dump on
    make verify-user_uart SIM=GL DUMP=OFF      - Standalone user uart-0 test using user risc core with gatelevel netlist
    make verify-user_uart SIM=GL DUMP=ON       - Standalone user uart-0 test using user risc core with gatelevel netlist and waveform on

Running RTL to GDS flows

  • First run the individual macro file
  • Last run the user_project_wrapper
   cd openlane
   make pinmux
   make qspim_top
   make uart_i2cm_usb_spi_top
   make wb_host
   make wb_interconnect
   make ycr_intf
   make ycr_core_top
   make ycr_iconnect
   make user_project_wrapper

Timing Analysis

Timing Analysis setup

   make setup-timing-scripts
   make install
   make install_mcw

his will update Caravel design files and install the scripts for running timing.

Running Timing Analysis

make extract-parasitics
make create-spef-mapping
make caravel-sta

Other Miscellaneous Targets

The makefile provides a number of useful that targets that can run LVS, DRC, and XOR checks on your hardened design outside of openlane’s flow.

Run make help to display available targets.

Run lvs on the mag view,

make lvs-<macro_name>

Run lvs on the gds,

make lvs-gds-<macro_name>

Run lvs on the maglef,

make lvs-maglef-<macro_name>

Run drc using magic,

make drc-<macro_name>

Run antenna check using magic,

make antenna-<macro_name>

Run XOR check,

make xor-wrapper

Tool Sets

Riscduino Soc flow uses Openlane tool sets.

  1. Synthesis
    1. yosys - Performs RTL synthesis
    2. abc - Performs technology mapping
    3. OpenSTA - Pefroms static timing analysis on the resulting netlist to generate timing reports
  2. Floorplan and PDN
    1. init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
    2. ioplacer - Places the macro input and output ports
    3. pdn - Generates the power distribution network
    4. tapcell - Inserts welltap and decap cells in the floorplan
  3. Placement
    1. RePLace - Performs global placement
    2. Resizer - Performs optional optimizations on the design
    3. OpenPhySyn - Performs timing optimizations on the design
    4. OpenDP - Perfroms detailed placement to legalize the globally placed components
  4. CTS
    1. TritonCTS - Synthesizes the clock distribution network (the clock tree)
  5. Routing
    1. FastRoute - Performs global routing to generate a guide file for the detailed router
    2. CU-GR - Another option for performing global routing.
    3. TritonRoute - Performs detailed routing
    4. SPEF-Extractor - Performs SPEF extraction
  6. GDSII Generation
    1. Magic - Streams out the final GDSII layout file from the routed def
    2. Klayout - Streams out the final GDSII layout file from the routed def as a back-up
  7. Checks
    1. Magic - Performs DRC Checks & Antenna Checks
    2. Klayout - Performs DRC Checks
    3. Netgen - Performs LVS Checks
    4. CVC - Performs Circuit Validity Checks

How To Contribute

We are looking for community help in following activity, interested user can ping me in efabless slack platform

  • Analog Design - ADC, DAC, PLL,
  • Digital Design - New IP Integration, Encription,DSP, DMA controller, 10Mb MAC, Floating point functions
  • Verification - Improving the Verification flow
  • Linux Porting - Build Root integration
  • Arudino Software Update - Tool Customisation for Riscduino, Adding additional plug-in and Riscv compilation support
  • Riscv Simulator - integration to Riscduino
  • Any other ideas

Contacts

Reference

Youtube video on Riscduino

News on Riscduino