Riscduino Peripheral Extension-1 SOC
Permission to use, copy, modify, and/or distribute this soc for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOC IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOC INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOC.
This is chip is add-on to our Riscduino SCORE/DCORE/QCORE Chip set. As there are no free space in the previous chip and this chip will be host additional function like mac core, stepper motor and new feature as needed. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.
* Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
* 100MB/10MB MAC core
* 4 pin Stepper Motor controller
* 8 x 2KB SRAM with MBIST controller
* Open-source tool set
* simulation - iverilog
* synthesis - yosys
* backend/sta - openlane tool set
* Verification suite provided.
MPW | Tape-out | Project Name | Project Details | Github | Efabless | Tapeout Link |
MPW-2 | 18-June-2021 | YiFive | Single 32bit RISCV core without cache + SDRAM Controller + WB Interconnect | Link | Link | Link |
MPW-3 | 15-Nov-2021 | Riscduino | Single 32bit RISCV core without cache + Onchip SRAM + WB Interconnect | Link | Link | Link |
MPW-4 | 31-Dec-2021 | Riscduino-R1 | Single 32bit RISCV core with cache + Onchip SRAM + WB Inter Connect | Link | Link | Link |
MPW-5 | 21-Mar-2022 | Riscduino-DCORE (D0) | Dual 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar | Link | Link | Link |
MPW-5 | 21-Mar-2022 | Riscduino-QCORE (Q0) | Quad 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar | Link | Link | Link |
MPW-6 | 07-June-2022 | Riscduino-SCORE (S3) | Single 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar | Link | Link | Link |
MPW-6 | 07-June-2022 | Riscduino-DCORE (D1) | Dual 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar | Link | Link | Link |
MPW-6 | 07-June-2022 | Riscduino-QCORE (Q1) | Quad 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar | Link | Link | Link |
MPW-7 | 12-Sept-2022 | Riscduino-SCORE (S4) | Single 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar | Link | Link | Link |
MPW-7 | 12-Sept-2022 | Riscduino-DCORE (D3) | Dual 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar | Link | Link | Link |
MPW-7 | 12-Sept-2022 | Riscduino-QCORE (Q1) | Quad 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar | Link | Link | Link |
EXT MAP | Target IP |
0x3008_0000 to 0x3008_FFFF | WB_HOST |
0x300C_0000 to 0x300C_FFFF | LBIST |
0x3000_0000 to 0x3000_00FF | GLBL |
0x3000_0100 to 0x3000_01FF | MAC |
0x3000_0200 to 0x3000_02FF | MBIST-0 |
0x3000_0300 to 0x3000_03FF | MBIST-1 |
0x3000_2000 to 0x3000_27FF | SRAM-0 |
0x3000_2800 to 0x3000_2FFF | SRAM-1 |
0x3000_3000 to 0x3000_37FF | SRAM-2 |
0x3000_3800 to 0x3000_3FFF | SRAM-3 |
0x3000_4000 to 0x3000_47FF | SRAM-4 |
0x3000_4800 to 0x3000_4FFF | SRAM-5 |
0x3000_5000 to 0x3000_57FF | SRAM-6 |
0x3000_5800 to 0x3000_5FFF | SRAM-7 |
Block | Total Cell | Combo | Seq | Utilization |
---|---|---|---|---|
MAC | 7350 | 5657 | 1693 | 35% |
MBSIT_WRAPPER * 2 | 4361 | 2720 | 641 | 35% |
WB_INTC | 5126 | 4133 | 993 | 16% |
WB_HOST | 6218 | 4868 | 1350 | 35% |
PINMUX | 3333 | 2589 | 744 | 35% |
NORTH-REPEATER | 245 | 245 | 0 | 20% |
SOUTH-REPEATER | 431 | 431 | 0 | 20% |
EAST-REPEATER | 111 | 111 | 0 | 20% |
WEST-REPEATER | 153 | 153 | 0 | 20% |
TOTAL | 31689 | 25627 | 6062 |
The simulation package includes the following tests:
#Timing Analysis
make setup-timing-scripts
make install
make install_mcw
his will update Caravel design files and install the scripts for running timing.
make extract-parasitics
make create-spef-mapping
make caravel-sta
#Other Miscellaneous Targets The makefile provides a number of useful that targets that can run LVS, DRC, and XOR checks on your hardened design outside of openlane’s flow.
Run make help to display available targets.
Run lvs on the mag view,
make lvs-<macro_name>
Run lvs on the gds,
make lvs-gds-<macro_name>
Run lvs on the maglef,
make lvs-maglef-<macro_name>
Run drc using magic,
make drc-<macro_name>
Run antenna check using magic,
make antenna-<macro_name>
Run XOR check,
make xor-wrapper
Riscduino Soc flow uses Openlane tool sets.
yosys
- Performs RTL synthesisabc
- Performs technology mappingOpenSTA
- Pefroms static timing analysis on the resulting netlist to generate timing reportsinit_fp
- Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)ioplacer
- Places the macro input and output portspdn
- Generates the power distribution networktapcell
- Inserts welltap and decap cells in the floorplanRePLace
- Performs global placementResizer
- Performs optional optimizations on the designOpenPhySyn
- Performs timing optimizations on the designOpenDP
- Perfroms detailed placement to legalize the globally placed componentsTritonCTS
- Synthesizes the clock distribution network (the clock tree)FastRoute
- Performs global routing to generate a guide file for the detailed routerCU-GR
- Another option for performing global routing.TritonRoute
- Performs detailed routingSPEF-Extractor
- Performs SPEF extractionMagic
- Streams out the final GDSII layout file from the routed defKlayout
- Streams out the final GDSII layout file from the routed def as a back-upMagic
- Performs DRC Checks & Antenna ChecksKlayout
- Performs DRC ChecksNetgen
- Performs LVS ChecksCVC
- Performs Circuit Validity ChecksApache License Version 2.0, January 2004 http://www.apache.org/licenses/ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 1. Definitions. "License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document. "Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License. "Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. For the purposes of this definition, "control" means (i) the power, direct or indirect, to cause the direction or management of such entity, whether by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity. 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