Riscduino Peripheral Extension-1 SOC


Permission to use, copy, modify, and/or distribute this soc for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.

THE SOC IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOC INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOC.

    * Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
    * 100MB/10MB MAC core
    * 4 pin Stepper Motor controller
    * 8 x 2KB SRAM with MBIST controller
    * Open-source tool set
       * simulation - iverilog
       * synthesis  - yosys
       * backend/sta - openlane tool set
    * Verification suite provided.

   make setup-timing-scripts
   make install
   make install_mcw

make extract-parasitics
make create-spef-mapping
make caravel-sta

make lvs-<macro_name>

make lvs-gds-<macro_name>

make lvs-maglef-<macro_name>

make drc-<macro_name>

make antenna-<macro_name>

make xor-wrapper

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