RISCDUINO Score

  4.6.1  June 24,2022, Dinesh A
         First fully arduino compatible based verification 
         test case arudino_risc_boot added
  4.6    June 13 2022, Dinesh A                               
         1. icache and dcache bypass config addded            
  4.5    June 2 2022, Dinesh A                                
         1. DFFRAM Replaced by SRAM                           
  4.4    May 29 2022, Dinesh A                                
         1. Digital PLL integrated and clock debug signal add 
           @digitial io [33] port                             
  4.3    May 24 2022, Dinesh A                                
         Re targetted the design to mpw-6 tools set and risc  
         core logic are timing optimized to 100mhz            
  4.2    April 6 2022, Dinesh A                               
         1. SSPI CS# increased from 1 to 4                    
         2. uart port increase to two                         
  3.9    Mar 16 2022, Dinesh A                                
         1. 3 Timer added                                     
         2. Pinmux Register address movement                  
         3. Risc fuse_mhartid is removed and internal tied    
            inside risc core                                  
         4. caravel wb addressing issue restrict to 0x300FFFFF
  3.8    Mar 10 2022, Dinesh A                                
         1. usb chip select bug inside uart_* wrapper         
         2. in wb_host, increased usb clk ctrl to 4 to 8 bit  
  3.7    Mar 2 2022, Dinesh A                                 
           1.   qspi cs# port mapping changed from io 28:25 to 25:28
           2.   sspi, bug fix in reg access and endian support added
           3.   Wishbone interconnect now support cross-connect     
          feature                                             
  3.6    Feb 19, Dinesh A                                     
           A.  Changed Module: wb_host                            
           wishbone slave clock generation config increase from   
           3 to 4 bit support clock source selection              
           B.  Changed Module: qspim                              
            1. Bug fix in spi rise and fall pulse relation w.r.t  
               spi_clk. Note: Previous version work only with     
               spi clock config = 0x2                             
            2. spi_oen generation fix for different spi mode      
            3. spi_csn de-assertion fix for different spi clk div 
  3.5  Feb 16, Dinesh A                                     
           As SRAM from sky130A is not yet qualified,             
           Following changes are done                             
           A. riscv core cache and tcm interface changed to dffram 
           B. removed the mbist controller + 4 SRAM               
           C. mbist controller slave port in wb_intern removed    
           D. Pinmux mbist port are removed                       
           E. mbist related buffering are removed at wb_inter     
  3.4  Feb 14, 2022, Dinesh A                               
       burst mode supported added in imem buffer inside     
       riscv core                                           
          We have created seperate repo from this onwards           
            SRAM based SOC is spin-out to                           
            dineshannayya/riscduino_sram.git                        
          This repo will remove mbist + SRAM and RISC SRAM will be  
          replaced with DFRAM                                       
  3.3  Feb 08, 2022, Dinesh A                               
       support added spisram support in qspim ip            
       There are 4 chip select available in qspim           
       CS#0/CS#1 targeted for SPI FLASH                     
       CS#2/CS#3 targeted for SPI SRAM                      
  3.2  Feb 02, 2022, Dinesh A                               
       Bug fix around icache/dcache and wishbone burst      
       access clean-up                                      
  3.1  Jan 15, 2022, Dinesh A                               
       Major changes in qspim logic to handle special mode  
  3.0  Jan 14, 2022, Dinesh A                               
       Moving from riscv core from syntacore/scr1 to         
       yfive/ycr1 on sankranti 2022 (A Hindu New Year)       
  2.6  Jan 08, 2022, Dinesh A                               
       Pinmux Interrupt Logic change                         
  2.5  Jan 06, 2022, Dinesh A                               
       TCM RAM Bug fix inside syntacore                       
  2.4  Jan 01, 2022, Dinesh A                               
        LA[0] is added as soft reset option at wb_port         
  2.3  Dec 24, 2021, Dinesh A                               
       UART Master added with message handler at wb_host       
  2.2  Dec 20, 2021, Dinesh A                               
       1. MBIST design issue fix for yosys                     
       2. Full chip Timing and Transition clean-up                               
  2.1  Dec 16, 2021, Dinesh A                               
       1.4 MBIST controller changed to single one              
       2.Added one more SRAM to TCM memory                     
       3.WishBone Interconnect chang to take care mbist changes
       4.Pinmux change to take care of mbist changes           
  2.0  Dec 14, 2021, Dinesh A                               
       Added two more 2K SRAM added into Wishbone Interface 
  1.9  Dec 11, 2021, Dinesh A                               
       2 x 2K SRAM added into Wishbone Interface            
       Temporary ADC block removed                          
  1.8  Nov 23, 2021, Dinesh A                               
        Three Chip Specific Signature added at PinMux Reg   
        reg_22,reg_23,reg_24                                
  1.7   Nov 15, 2021, Dinesh A                              
         Bug fix in clk_ctrl High/Low counter width         
         Removed sram_clock                                 
  1.6   Nov 14, 2021, Dinesh A                              
        Major bug, clock divider inside the wb_host reset   
        connectivity open is fixed                          
  1.5 - 6th Nov 2021, Dinesh A                              
        Clock Skew block moved inside respective block due  
        to top-level power hook-up challenges for small IP  
  1.4 - 13th Oct 2021, Dinesh A                             
        Basic verification and Synthesis cleanup            
  1.3 - 30th Sept 2021, Dinesh.A                            
        2KB SRAM Interface added to RISC Core               
  1.2 - 29th Sept 2021, Dinesh.A                            
        1. copied the repo from yifive and renames as       
           riscdunino                                       
        2. Removed the SDRAM controlled                     
        3. Added PinMux                                     
        4. Added SAR ADC for 6 channel                      
  1.1 - 1st Aug 2021, Dinesh A                              
        usb1.1 host integrated part of uart_i2cm_usb module,
        due to number of IO pin limitation,                 
        Only UART/I2C/USB selected based on config mode     
  1.0 - 28th July 2021, Dinesh A                            
        i2cm integrated part of uart_i2cm module,           
        due to number of IO pin limitation,                 
        Only UART OR I2C selected based on config mode      
  0.9 - 7th July 2021, Dinesh A                             
        Removed 2 Unused port connection io_in[31:30] to    
        spi_master to avoid lvs issue                       
  0.8 - 6th July 2021, Dinesh A                             
        For Better SDRAM Interface timing we have taping    
        sdram_clock goint to io_out[29] directly from       
        global register block, this help in better SDRAM    
        interface timing control                            
  0.7 - 28th June 2021, Dinesh A                            
        wb_interconnect master port are interchanged for    
        better physical placement.                          
        m0 - External HOST                                  
        m1 - RISC IMEM                                      
        m2 - RISC DMEM                                      
  0.6 - 27th June 2021, Dinesh A                            
        Digital core level tie are moved inside IP to avoid 
        power hook up at core level                         
        u_risc_top - test_mode & test_rst_n                 
        u_intercon - s*_wbd_err_i                           
        unused wb_cti_i is removed from u_sdram_ctrl        
  0.5 - 25th June 2021, Dinesh A                            
        Since carvel gives only 16MB address space for user 
        space, we have implemented indirect address select  
        with 8 bit bank select given inside wb_host         
        core Address = {Bank_Sel[7:0], Wb_Address[23:0]     
        caravel user address space is                       
        0x3000_0000 to 0x30FF_FFFF                          
  0.4 - 25th June 2021, Dinesh A                            
        Moved the pad logic inside sdram,spi,uart block to  
        avoid logic at digital core level                   
  0.3 - 20th June 2021, Dinesh A                            
         1. uart core is integrated                         
         2. 3rd Slave ported added to wishbone interconnect 
  0.2 - 17th June 2021, Dinesh A                            
         1. In risc core, wishbone and core domain is          
            created                                            
         2. cpu and rtc clock are generated in glbl reg block  
         3. in wishbone interconnect:- Stagging flop are added 
            at interface to break wishbone timing path         
         4. buswidth warning are fixed inside spi_master       
         modified rtl files are                                
            verilog/rtl/digital_core/src/digital_core.sv       
            verilog/rtl/digital_core/src/glbl_cfg.sv           
            verilog/rtl/lib/wb_stagging.sv                     
            verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv 
            verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv 
            verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv  
            verilog/rtl/user_project_wrapper.v                 
            verilog/rtl/wb_interconnect/src/wb_interconnect.sv 
            verilog/rtl/spi_master/src/spim_clkgen.sv          
            verilog/rtl/spi_master/src/spim_ctrl.sv            
  0.1 - 16th Feb 2021, Dinesh A                             
        Initial integration with Risc-V core +              
        Wishbone Cross Bar + SPI  Master                    

                                 Apache License
                           Version 2.0, January 2004
                        http://www.apache.org/licenses/

   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION

   1. Definitions.

      "License" shall mean the terms and conditions for use, reproduction,
      and distribution as defined by Sections 1 through 9 of this document.

      "Licensor" shall mean the copyright owner or entity authorized by
      the copyright owner that is granting the License.

      "Legal Entity" shall mean the union of the acting entity and all
      other entities that control, are controlled by, or are under common
      control with that entity. For the purposes of this definition,
      "control" means (i) the power, direct or indirect, to cause the
      direction or management of such entity, whether by contract or
      otherwise, or (ii) ownership of fifty percent (50%) or more of the
      outstanding shares, or (iii) beneficial ownership of such entity.

      "You" (or "Your") shall mean an individual or Legal Entity
      exercising permissions granted by this License.

      "Source" form shall mean the preferred form for making modifications,
      including but not limited to software source code, documentation
      source, and configuration files.

      "Object" form shall mean any form resulting from mechanical
      transformation or translation of a Source form, including but
      not limited to compiled object code, generated documentation,
      and conversions to other media types.

      "Work" shall mean the work of authorship, whether in Source or
      Object form, made available under the License, as indicated by a
      copyright notice that is included in or attached to the work
      (an example is provided in the Appendix below).

      "Derivative Works" shall mean any work, whether in Source or Object
      form, that is based on (or derived from) the Work and for which the
      editorial revisions, annotations, elaborations, or other modifications
      represent, as a whole, an original work of authorship. For the purposes
      of this License, Derivative Works shall not include works that remain
      separable from, or merely link (or bind by name) to the interfaces of,
      the Work and Derivative Works thereof.

      "Contribution" shall mean any work of authorship, including
      the original version of the Work and any modifications or additions
      to that Work or Derivative Works thereof, that is intentionally
      submitted to Licensor for inclusion in the Work by the copyright owner
      or by an individual or Legal Entity authorized to submit on behalf of
      the copyright owner. For the purposes of this definition, "submitted"
      means any form of electronic, verbal, or written communication sent
      to the Licensor or its representatives, including but not limited to
      communication on electronic mailing lists, source code control systems,
      and issue tracking systems that are managed by, or on behalf of, the
      Licensor for the purpose of discussing and improving the Work, but
      excluding communication that is conspicuously marked or otherwise
      designated in writing by the copyright owner as "Not a Contribution."

      "Contributor" shall mean Licensor and any individual or Legal Entity
      on behalf of whom a Contribution has been received by Licensor and
      subsequently incorporated within the Work.

   2. Grant of Copyright License. Subject to the terms and conditions of
      this License, each Contributor hereby grants to You a perpetual,
      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
      copyright license to reproduce, prepare Derivative Works of,
      publicly display, publicly perform, sublicense, and distribute the
      Work and such Derivative Works in Source or Object form.

   3. Grant of Patent License. Subject to the terms and conditions of
      this License, each Contributor hereby grants to You a perpetual,
      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
      (except as stated in this section) patent license to make, have made,
      use, offer to sell, sell, import, and otherwise transfer the Work,
      where such license applies only to those patent claims licensable
      by such Contributor that are necessarily infringed by their
      Contribution(s) alone or by combination of their Contribution(s)
      with the Work to which such Contribution(s) was submitted. If You
      institute patent litigation against any entity (including a
      cross-claim or counterclaim in a lawsuit) alleging that the Work
      or a Contribution incorporated within the Work constitutes direct
      or contributory patent infringement, then any patent licenses
      granted to You under this License for that Work shall terminate
      as of the date such litigation is filed.

   4. Redistribution. You may reproduce and distribute copies of the
      Work or Derivative Works thereof in any medium, with or without
      modifications, and in Source or Object form, provided that You
      meet the following conditions:

      (a) You must give any other recipients of the Work or
          Derivative Works a copy of this License; and

      (b) You must cause any modified files to carry prominent notices
          stating that You changed the files; and

      (c) You must retain, in the Source form of any Derivative Works
          that You distribute, all copyright, patent, trademark, and
          attribution notices from the Source form of the Work,
          excluding those notices that do not pertain to any part of
          the Derivative Works; and

      (d) If the Work includes a "NOTICE" text file as part of its
          distribution, then any Derivative Works that You distribute must
          include a readable copy of the attribution notices contained
          within such NOTICE file, excluding those notices that do not
          pertain to any part of the Derivative Works, in at least one
          of the following places: within a NOTICE text file distributed
          as part of the Derivative Works; within the Source form or
          documentation, if provided along with the Derivative Works; or,
          within a display generated by the Derivative Works, if and
          wherever such third-party notices normally appear. The contents
          of the NOTICE file are for informational purposes only and
          do not modify the License. You may add Your own attribution
          notices within Derivative Works that You distribute, alongside
          or as an addendum to the NOTICE text from the Work, provided
          that such additional attribution notices cannot be construed
          as modifying the License.

      You may add Your own copyright statement to Your modifications and
      may provide additional or different license terms and conditions
      for use, reproduction, or distribution of Your modifications, or
      for any such Derivative Works as a whole, provided Your use,
      reproduction, and distribution of the Work otherwise complies with
      the conditions stated in this License.

   5. Submission of Contributions. Unless You explicitly state otherwise,
      any Contribution intentionally submitted for inclusion in the Work
      by You to the Licensor shall be under the terms and conditions of
      this License, without any additional terms or conditions.
      Notwithstanding the above, nothing herein shall supersede or modify
      the terms of any separate license agreement you may have executed
      with Licensor regarding such Contributions.

   6. Trademarks. This License does not grant permission to use the trade
      names, trademarks, service marks, or product names of the Licensor,
      except as required for reasonable and customary use in describing the
      origin of the Work and reproducing the content of the NOTICE file.

   7. Disclaimer of Warranty. Unless required by applicable law or
      agreed to in writing, Licensor provides the Work (and each
      Contributor provides its Contributions) on an "AS IS" BASIS,
      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
      implied, including, without limitation, any warranties or conditions
      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
      PARTICULAR PURPOSE. You are solely responsible for determining the
      appropriateness of using or redistributing the Work and assume any
      risks associated with Your exercise of permissions under this License.

   8. Limitation of Liability. In no event and under no legal theory,
      whether in tort (including negligence), contract, or otherwise,
      unless required by applicable law (such as deliberate and grossly
      negligent acts) or agreed to in writing, shall any Contributor be
      liable to You for damages, including any direct, indirect, special,
      incidental, or consequential damages of any character arising as a
      result of this License or out of the use or inability to use the
      Work (including but not limited to damages for loss of goodwill,
      work stoppage, computer failure or malfunction, or any and all
      other commercial damages or losses), even if such Contributor
      has been advised of the possibility of such damages.

   9. Accepting Warranty or Additional Liability. While redistributing
      the Work or Derivative Works thereof, You may choose to offer,
      and charge a fee for, acceptance of support, warranty, indemnity,
      or other liability obligations and/or rights consistent with this
      License. However, in accepting such obligations, You may act only
      on Your own behalf and on Your sole responsibility, not on behalf
      of any other Contributor, and only if You agree to indemnify,
      defend, and hold each Contributor harmless for any liability
      incurred by, or claims asserted against, such Contributor by reason
      of your accepting any such warranty or additional liability.

   END OF TERMS AND CONDITIONS

   APPENDIX: How to apply the Apache License to your work.

      To apply the Apache License to your work, attach the following
      boilerplate notice, with the fields enclosed by brackets "[]"
      replaced with your own identifying information. (Don't include
      the brackets!)  The text should be enclosed in the appropriate
      comment syntax for the file format. We also recommend that a
      file or class name and description of purpose be included on the
      same "printed page" as the copyright notice for easier
      identification within third-party archives.

   Copyright [yyyy] [name of copyright owner]

   Licensed under the Apache License, Version 2.0 (the "License");
   you may not use this file except in compliance with the License.
   You may obtain a copy of the License at

       http://www.apache.org/licenses/LICENSE-2.0

   Unless required by applicable law or agreed to in writing, software
   distributed under the License is distributed on an "AS IS" BASIS,
   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   See the License for the specific language governing permissions and
   limitations under the License.