OSIRIS I: A Low-Power 32-bit RISC Core Processor

Introduction

This is a design of a 5-stage pipeline 32-bit RISC core with 16 general-purpose registers (x0-x15), where x0 is a dedicated ZERO register. The program counter PC is a special-purpose 32-bit register. That can address at most 2³² instructions. All instructions are 32-bit. There are six instruction formats: R-type, I-type, S-type, B-Type, J-type, and U-type.

Refer to README for this project documentation.