SoomRV-GF180MCU

The Linux-capable, out-of-order SoomRV rv32i core on GF180MCU.

General

The SoomRV RISC-V core was first developed for the OpenMPW-7 shuttle. Since then, development has steadily continued. Most importantly, SoomRV now implements the RISC-V Privileged Spec including virtual memory, enabling it to run Linux. In addition, countless microarchitectural details have been optimized or re-implemented, significantly improving performance and area-efficiency.

Due to size limitations on GF180MCU, this is a rather small instantiation of the core. Still, 2-wide superscalar OoO execution is possible, with a 32 entry ROB and 2KiB each of instruction and data caches. Registers are re-named, and instructions can be re-ordered arbitrarily by the Issue Queues. Two integer, or one integer and one memory access instruction can be executed simultaneously. SoomRV's AXI memory interface is converted to a simple 32-bit bus on the Caravel GPIO pins. External memory and MMIO devices can be connected to this bus via a support FPGA.

Features

• 2-wide superscalar out-of-order execution
  • 2x Integer ALU, 1x LD/ST AGU
  • 2x 4 entry issue queues
  • 8 entry load and store queues
  • Fully out-of-order memory, in-order for MMIO regions
  • Non-blocking cache and TLB misses
• Implements RISC-V Privileged Spec
  • sv32 virtual memory
  • boots regular Linux
• Memory
  • Instruction and Data Caches
    • 2 KiB each
    • direct-mapped VIPT
  • 64MiB of external (cacheable) memory and MMIO
    • Access via simple bidirectional 32-bit bus on IO pins
• Branch Prediction
  • 32 entry Branch Target Buffer
    • 0-cycle branch latency on BTB hit
    • 3-cycle branch latency on BTB miss
  • TAGE direction predictor
    • 256 bimodal counters as base predictor
    • 2x 32-entry tagged predictors with 6 and 12 bits of global history respectively
  • Return Predictor
    • 4 entry return stack
    • 4 entry return recovery queue

Verification

Verification of SoomRV was performed on the following three levels:

1. Verilator RTL Simulation with co-simulation against RISC-V ISA Sim (Spike).
   • SoomRV execution is identical to Spike during Linux boot and many other tests
   • Implemented in the SoomRV repo and the included SoomRV/ subtree.
2. IVerilog RTL/GL Simulation of standalone SoomRV core
   • RTL Simulation after conversion from SystemVerilog with sv2v, GL simulation after synthesis with OpenLane
   • Implemented in verilog/dv/soomrv (run make/make all_rtl/make all_gl or e.g. make ../programs/virtual_mem_gl for a specific program)
3. CocoTB RTL Simulation of SoomRV integrated into Caravel
   • Verification of logic analyzer probes and tri-state GPIO for bidirectional bus
   • Implemented in verilog/dv/cocotb

SoomRV has also been successfully synthesized for and run on FPGA via the same sv2v+yosys workflow used here (see SoomRV-Arty), though in a somewhat different configuration.

Build Process

1. Go into the SoomRV/ subtree and run make verilog to convert SoomRV's SystemVerilog sources to a single core.v Verilog file.
2. Copy SoomRV/core.v to verilog/rtl/core.v
3. Run patch verilog/rtl/core.v verilog/dv/soomrv/iverilog_setup.patch.
   These patches are just for simulation and do not affect synthesis, but should always be applied anyways to keep source code identical between the two.
4. Run make user_project_wrapper