SOC BAASED Multi Projects Chip:

SOC BAASED Multi Projects Chip:

Cryptographic Core with Delicated Wishbone to UART and TWO VGA Display Projects


The project presents an implementation of SHA-1 and SHA-256 [validity used in encryption, decryption, and key generation] cryptographic algorithms on open-source ASIC implementation. The project, combined with a RISC-V processor, can be used to test post-quantum algorithms. The said crypto cores will be used to encrypt and decrypt data and generate pseudorandom number generation. The main focus will be on the time rate and security of key and data transfer. Later on, the design can be further extended and checked for blockchain algorithms or mining as test case because the said design has everything, such as modules like SHA-256 and a processor (RISC-V), to validate some of the blockchain algorithms. The whole system is designed to ensure that the design works correctly when used on a real chip.

	
The Following Cores and Submdoules are implemented in this SOC based PROJECT.


1	XTEA
2	SHA1
3	SHA256
4 	WBUART
5	VGA Based GAME
6	VGA Based real-time Clock Display

1 XTEA

xtea.v

Top level wrapper for the XTEA block cipher core.

xtea_core.v

XTEA block cipher core.

2 SHA1

  sha1.v

Top level wrapper for the SHA-1 hash function providing a simple memory like interface with 32 bit data access.

sha1_w_mem_reg.v

The SHA-1 W memory. This memory includes functionality to expand the block into 80 words.

sha1_core.v

Verilog 2001 implementation of the SHA-1 hash function. This is the internal core with wide interfaces.

3 SHA256

sha256.v

Top level wrapper for the SHA-256 hash function providing a simple memory like interface with 32 bit data access.

sha256_core.v

Verilog 2001 implementation of the SHA-256 hash function. This is the internal core with wide interfaces.

sha256_w_mem_regs.v

The W memory. This version uses 16 32-bit registers as a sliding window to generate the 64 words.

sha256_k_constants.v

The table K with constants in the SHA-256 hash function.

4 WBUART [Delicated Wishbone to UART for FAST Transmission OF DATA for Crypto-Cores]

The Universal Asynchronous Serial Transport, or UART, has become quite the common protocol devices. It is simple to wire up, easy to use, and easy to process. This core provides one implementation of the logic necessary to use such a communications scheme. While you are likely to find many UART examples out there, this particular UART implementation offers something many of these other examples do not: a Verilator simulation capability. This will allow the user to connect, via a TCP/IP port or a telnet application, to the UART of their desired chip. As a result, full two-way interaction can be had between a simulation and a terminal or other port. Indeed, this may even be sufficient to connect a CPU, capable of running Linux, to a terminal to verify that yes it can truly run Linux–all within Verilator. As a final addition, there are four files in the test bench section which can be used as top–level design files to prove whether or not the serial port on a given circuit board works.