thorstenknoll /   AudioChip

Created
Maintained by thorstenknoll
An electronic instrument is the goal of this project. AudioChip will become a sound producing part for modular synthesizers. The Eurorack format has become quite popular with the synthesizer DIY makerscene around the world. This will contribute to this development.
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Thorsten Knoll committed 4 months ago

AudioChip

License UPRJ_CI Caravel Build

Description

This is an AudioChip that outputs two Audiosignals as PWM. It can be used as a audio generating device for electronic instruments, namely modular synthesizers. It is planned to build a Eurorack module for a modular synthesizer around this mikrochip. The inputs and outputs are designed to fit into the concept of such instruments. The source code of AudioChip is written in spinalHDL and resides here in branch gf180:

https://github.com/ThorKn/icestick_spinalHDL_pwmAudio

Prototype

A FPGA based prototype of this chip was done and tested with various other parts of Eurorack modular synthesizers.

Alt text

Features

Outputs

  • PWM 1: Square Wave with ADSR envelope for amplitude attenuation
  • PWM 2: Ramp Wave

The PWM frequency carrier frequency (f_car) is defined by the clock frequency (f_clk) divided by the max value of the PWM resolution width of 8 bit (pwm_res = 255):

fcar = f_clk / pwm_res

Example: With a clock of 12MHz, the PWM runs at roughly 47KHz.

Inputs

  • Audio frequency: 12 bit resolution, parallel pins
  • Note length: 3 bit as a multiplicator for the ADSR envelope length
  • ADSR switch: On/Off for the ADSR envelope generator. Off means the audio output has a constant amplitude
  • Loop: On/Off for the ADSR Looping function. Off means the Trigger input is enabled
  • Trigger: Starts a run through the ADSR state machine. Only enabled when Loop is Off
  • ADRS choice: 3 bit for choosing different ADSR envelopes

Generated Verilog

The verilog gets generated by running the scala build tool (sbt). This is not part of this AudioChip repository. The verilog code got copied over to here and put inside the caravel for the GF180 shuttle run.

Simulation and Testing

The simulation of the circuit is done in spinalHDL. The sim is clockdriven and outputs a .vcd to view in GTKwave. The PWM output is easy to observe and analyse.

The AudioChip design runs on an Lattice IceStick FPGA and does excatly what it should do. The inputs and outputs got tested and do function in the way they are intended.

The IOs, names and defines of the AudioChip

Name IO define
reset wb_rst_i none, internal
clk wb_clk_i none, internal
io_pwm_1 io_out[10] GPIO_MODE_USER_STD_OUTPUT
io_pwm_2 io_out[11] GPIO_MODE_USER_STD_OUTPUT
io_frequency io_in[37:26] GPIO_MODE_USER_STD_INPUT_PULLDOWN
io_note_length io_in[25:23] GPIO_MODE_USER_STD_INPUT_PULLDOWN
io_adsr_switch io_in[22] GPIO_MODE_USER_STD_INPUT_PULLDOWN
io_loop io_in[21] GPIO_MODE_USER_STD_INPUT_PULLDOWN
io_trigger io_in[20] GPIO_MODE_USER_STD_INPUT_PULLDOWN
io_adsr_choice io_in[19:17] GPIO_MODE_USER_STD_INPUT_PULLDOWN
io_oeb_high io_oeb[37:17] permanent set to high in PWMaudio.v
io_oeb_low io_oeb[11:10] permament set to low in PWMaudio.v

All other IOs above [4] are defined as GPIO_MODE_USER_STD_INPUT_PULLDOWN and are not used in the AudioChip design. The IOs [4:0] are not touched.

A word about pmod_oeb

The only input and output wires of the caravel RISC-V need the oeb lines set (In = HIGH, Out = Low). This is not allowed to be done in the user_project_wrapper, so it went straight into the PWMaudio.v verilog, near to the top.