aidanoblepias
Aidan Oblepias • Joined 11 months ago
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forks/aidanoblepias/aidanoblepias/parity-checker-nd-aagl
This repository contains the Verilog implementation of a signal parity checker designed to be synthesized on the EFabless Caravel OpenLane flow. The circuit is intended for use with the Global Foundries gf180mcuD Process Development Kit as part of the coursework for CSE 30342 - Digital Integrated Circuits at the University of Notre Dame.