marwan_abbas

ac3e_chile_chipathon_team/AC3E_Open3LFCC_V2_repo

Open3LFCC_V2 and student projects

damor_rbz/AGANTItp0

AGANTIv0

smay26/analog_tester2

tester

amm_efabless/Anton-Test-UCLA-Makar-1

Test upload for Makar from UCLA - Slot1

amm_efabless/Anton-Test-UCLA-Makar-2

Test upload for Makar from UCLA - Slot2

thomasjagielski/async_md5_hasher

Asynchronous md5 hasher.

bharatpi/Bharat-Pi-Om

Risc V based MCU for tinkering labs and mini projects.

passant/caravel-dft

Caravel with DFT in the SoC and user project wrapper

passant/caravel-dft-upw

Caravel DFT with AES user project wrapper from OL2 tutorial

marwan_abbas/caravel_mini_2411

caravel mini project for aggregating the user projects into one project

aidanmedcalf/ci2406-fgcaptest-drc-test

ci2406-fgcaptes varac.5 DRC test

amm_efabless/ci2409_counter_7seg

Caravel test project from caravel_user_project with 7seg decoder added.

amm_efabless/ci2409_counter_7seg_alt

Modified ci2409_counter_7seg to support output switching to alternate outputs (including all 4 hex digits)

amm_efabless/ci2409_counter_and_vga2

Revert to earlier version of ci2409_counter_and_vga with better timing

amm_efabless/ci2409_counter_and_vga3

Anton's Efabless example project: counter example + VGA "raybox-zero" demo

amm_efabless/ci2409_test

Jeff's https://github.com/jeffdi/ci2409_test/ based on caravel_user_project

monktech/Cientera

Space Microcontroller

jeff/CS_Test_Project3

A test of the OpenLane 2 flow at CS.

amm_efabless/CUP_decap_test

Testing default decap cell behaviour with precheck/tapeout on Platform

datnassoc/Data-Encryption-POC

Advanced Encryption in ASIC for Datacenters

elamdf/EECS151T

placeholder- undergrad-run educational SoC tapeout

musabfarooq96/FIR_Imaging

FIR imaging using devices in CMOS.

monktech/FuseEV

We combine new powertrains with classic car charm "Designing a classic car to run on electric is an art form and we aim to extend the life of your classic car by giving it a new sustainable lease of life"

olyanasab/g.to1

g.to1 ADC+TX

rodrigowue/IC1-CASS-2023

IC1-CASS-2023

niks0091/ISC-RF-Controller

We are designing RISC V based ISC RF Controller which we consider as Phase-1 of the development0

benisonpin/ISP_cteTWLCEO

Integrate the RISC-V & ISP pipeline

monktech/Ka-Naada

One keyboard for many Indic languagesKa-Naada is a unique patented keyboard layout design for Indic languages (Brahmi based), without clutter and overload of English language feature of ‘spelling’.

keysom_asic/Keysom-Butterfly

Keysom 11/24 tapeout 1

manishmahajan/LDPC_5G

LDPC Encoder Decoder

manishmahajan/LDPC_ENC_DEC

NR 5G 2_0_4 BG2

david_lindley/MacDuino1_2

This is a copy of the MacDuinol with fixed PSDM/NSDM in openrams, fixed two m2 spacing issues

dan20kim/Motion-Compensation-IC-v2

Motion Compensation IC

facundoaguirre/PUF_Design

Bistable Ring PUF

a_james/ReRAM_Crossbar

ReRAM crossbar Arrays for In-Memory Computing

kevinwguan/ReRAM-Crossbar-Array

ReRAM-Crossbar-Array

yonguk/RRAM-Memory

RRAM: Resistive random access memory using sky130 ReRAM The memory includes a ReRAM array, decoder, sense amplifier, and controller. Mixed-signal designs -digital part: controller -analog part: others Features Forming Write Read

xingsmart/RRAM_sindhu

digital ip, TDC DAC and NOC tet structures

marchuerta/RREFLECT

A pathtracing accelerator meant to render full light composition scenes more accurately than traditional ray tracing.

yangd333/RX-Receiver_Frontend

Simple RF Receiver front-end for WiFi 6 (5.925 GHz). Aims to improve linearity on LNA and Mixer.

burak_aykenar/SAKAv0.1

This is an embedded FPGA (eFPGA) IP project. The fabric netlist is generated by OpenFPGA framework. https://github.com/lnis-uofu/OpenFPGA This IP is designed by Yongatek Microelectronics. Yongatek Microelectronics provide a wide range of IC/ASIC/SoC/Chip Design, 5G/6G and Satellite Communications, Video Processing and IoT areas within the industry with an experienced and highly qualified R&D team. https://www.yongatek.com/ FPGA fabric consist of 6x6 complex logic blocks (CLB). Each CLB has 4 logic elements (LE). Each logic element has a LUT4 and a FF. Routing channels have 60 tracks: 6 L1, 6 L2 and 48 L4 track lengths. There are 24 IO blocks surrounding the fabric. Each IOB has 6 IO pins, a total of 144 pins. Pins are connected to logic analyzer (LA) of the management core and other 38 external IOs. You can contact through info@yongatek.com

christoph/ScoooterDexie

A security hardened RISC-V processor.

monktech/Smowcode

Smowcode – An industry-grade visual coding language for ESP32 & MSPM0+ micro-controllers.

efabless_common/snappy_tapeout

Snappy Project Tapeout

ymei/SNRLxP0

SNRLxP0 chip for efabless tapeout in sky130

tbeechem/SpecereThermVeh

This is a thermal test vehicle designed to assess optical thermometry methods and their applicability to logic.

passant/SRAM-TC

Test chip for S8TSSC

engrvip/ssp_testchip

This is the first testchip containing designs from KACST-SSP students.

Projects