mohamedkassem

monktech/FuseEV

We combine new powertrains with classic car charm "Designing a classic car to run on electric is an art form and we aim to extend the life of your classic car by giving it a new sustainable lease of life"

olyanasab/g.to1

g.to1 ADC+TX

rodrigowue/IC1-CASS-2023

IC1-CASS-2023

niks0091/ISC-RF-Controller

We are designing RISC V based ISC RF Controller which we consider as Phase-1 of the development0

benisonpin/ISP_cteTWLCEO

Integrate the RISC-V & ISP pipeline

monktech/Ka-Naada

One keyboard for many Indic languagesKa-Naada is a unique patented keyboard layout design for Indic languages (Brahmi based), without clutter and overload of English language feature of ‘spelling’.

keysom_asic/Keysom-Butterfly

Keysom 11/24 tapeout 1

manishmahajan/LDPC_5G

LDPC Encoder Decoder

manishmahajan/LDPC_ENC_DEC

NR 5G 2_0_4 BG2

amm_efabless/Ludwig-Anton-LC1

Ludwig-Anton-LC1

mohamedkassem/MK-ABC

MK-ABC

mohamedkassem/MKKCI2309

ABC

dan20kim/Motion-Compensation-IC-v2

Motion Compensation IC

facundoaguirre/PUF_Design

Bistable Ring PUF

mohamedkassem/qrwtw45y4w5y

erewrwerqw

a_james/ReRAM_Crossbar

ReRAM crossbar Arrays for In-Memory Computing

kevinwguan/ReRAM-Crossbar-Array

ReRAM-Crossbar-Array

yonguk/RRAM-Memory

RRAM: Resistive random access memory using sky130 ReRAM The memory includes a ReRAM array, decoder, sense amplifier, and controller. Mixed-signal designs -digital part: controller -analog part: others Features Forming Write Read

xingsmart/RRAM_sindhu

digital ip, TDC DAC and NOC tet structures

marchuerta/RREFLECT

A pathtracing accelerator meant to render full light composition scenes more accurately than traditional ray tracing.

yangd333/RX-Receiver_Frontend

Simple RF Receiver front-end for WiFi 6 (5.925 GHz). Aims to improve linearity on LNA and Mixer.

burak_aykenar/SAKAv0.1

This is an embedded FPGA (eFPGA) IP project. The fabric netlist is generated by OpenFPGA framework. https://github.com/lnis-uofu/OpenFPGA This IP is designed by Yongatek Microelectronics. Yongatek Microelectronics provide a wide range of IC/ASIC/SoC/Chip Design, 5G/6G and Satellite Communications, Video Processing and IoT areas within the industry with an experienced and highly qualified R&D team. https://www.yongatek.com/ FPGA fabric consist of 6x6 complex logic blocks (CLB). Each CLB has 4 logic elements (LE). Each logic element has a LUT4 and a FF. Routing channels have 60 tracks: 6 L1, 6 L2 and 48 L4 track lengths. There are 24 IO blocks surrounding the fabric. Each IOB has 6 IO pins, a total of 144 pins. Pins are connected to logic analyzer (LA) of the management core and other 38 external IOs. You can contact through info@yongatek.com

mohamedkassem/scfadFVAef

efEQFASFQW

christoph/ScoooterDexie

A security hardened RISC-V processor.

monktech/Smowcode

Smowcode – An industry-grade visual coding language for ESP32 & MSPM0+ micro-controllers.

efabless_common/snappy_tapeout

Snappy Project Tapeout

ymei/SNRLxP0

SNRLxP0 chip for efabless tapeout in sky130

tbeechem/SpecereThermVeh

This is a thermal test vehicle designed to assess optical thermometry methods and their applicability to logic.

passant/SRAM-TC

Test chip for S8TSSC

engrvip/ssp_testchip

This is the first testchip containing designs from KACST-SSP students.

passant/swift-V3

Swift redesign

samdlarson/test_chip_B_231105

Bare Die Version - Test Chip

samdlarson/test_chip_PV_231105

Packaged Version - Test Chip

mohamedkassem/TheSwitch

The Switch

mohamedkassem/TSRI1

al design tools continue to dramatically improve across multiple domains, from synthesis to place androute and verification, enabling faster turnaround times for large designs and shifting the innovation focal point for designers. The core concepts of digital design still taught in many introductory very large scale integration (VLSI) classes, such as logical effort and arithmetic unit design, are, today, automated, leav ing many lowlevel decisions to a tool informed by design constraints and outside the engineer’s hands. Due to the increase in both gates per design and productivity through automa tion, we are starting to see metrics, such as design effort and time to working silicon, compete with power, performance, and area. Along with the slowdown in Moore’s law, we are seeing an increase in interest in more softwarerelated career paths. As shown in Figure 1, there is evidence that students are voting with their feet and moving into co

niorcasitas07/UNIC-CASS_Ring_Oscillators

This repository includes the files related to the proposal entitled ‘Ring Oscillators Frequency degradation for Reliability characterization with Bias temperature instability (BTI) and hot carrier (HC) effects’ for UNICASS 2024.

ryanmprice/UTEP_CML_Sensor_Test_Article_17

Convergent Microsystems Lab Test article for sensor interfaces

a_aboulsaad/UW-EE437-SP24

This is a capstone course project led by Professor Jacques C. Rudell, along with the PhD candidate Ahmed R. Aboulsaad. The tape-out chip will include 4 projects designed by undergraduate students and graduate students: 1- Quantum Controller Receiver Project. 2- Audio Amplifier Project. 3- Bi-directional Wireline Chip Interface Project. 4- High Linearity N-Path Filter Project.

elpidakrp/UW-elpida

UW-elpida

vonbraunlabs/vbl-riscv-ci2406

VBL RISC-V

vonbraunlabs/vbl_riscv_slx

von Braun Labs RISC-V

vonbraunlabs/vbl-riscv-slx

von Braun Labs - RISCV

Projects