passant

Bassant Hassan • Joined a year ago

passant/3-IPs

Includes 3 different IPs; PSRAM controller, timer, and UART

passant/AES

AES accelerator example connected on the WB bus

passant/Clear

CLEAR is an Open Source FPGA-ASIC utilizing 9x9 eFPGA

passant/Counter-OL2

Counter user project example using OpenLane 2

passant/LDO1V8

A test chip including three 3.3 V to 1.8 V, 100 mA, LDO

passant/LDOR1V8E

A test chip including three 3.3 V to 1.8 V, logic-controlled LDOs