Dr. Skandha Deepsita • Joined 3 years ago

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This project is an implementation of approximate adder for error tolerant multimedia applications. The approximate single bit adder is built using which multi bit adder is built basing on the approximation factor. The delay chain is completely eliminated for the approximate part and is reduced by length k for accurate half of the n-bit approximate adder.
This project is implementation of approximate multiplier published in ACM TODAES journal 2021, titled "Energy Efficient Error Resilient Multiplier Using Low-power Compressors".
The sum of products circuits with four 8-bit inputs, approximate multiplier and approximate adder elements and 17 bit output with function Z=AB+CD