Power-optimized Exponential Golomb Decoder for H.264 Video DecodingAs a team committed to enhancing video playback performance through this project, our efforts stem from a deep understanding of the challenges faced by camera and object detection algorithms. By delivering an open-source, high-performance solution, we aspire to empower...
We propose to design a Bluetooth Low-Energy (BLE) Transmitter consisting of a Class-B CMOS Digitally Controlled Oscillator (DCO) and a Class-D Power Amplifier (PA) with on-chip matching designed to deliver 0 dBm to a 50 Ω load at maximum drain efficiency. In order to simplify the design, the first iteration will not include a PLL, only an...
Description of the Design Idea:*
The COordinate Rotation DIgital Computer (CORDIC) is a multiplier-less and hardware friendly circuit processor that uses shift-add operations to compute mathematical operations such as trigonometric functions, division, square root, and others. CORDIC is of high interest in many application domains such as...
Nano Electronics Bringing Undergraduate Learning Ahead (NEBULA) is a project from the Purdue Semiconductor Training And Readiness for Semiconductors (STARS) program that contains 12 early undergrad student projects.
In the contemporary landscape of computing, where data is vital, safeguarding its integrity is paramount. However, modern computing systems are under constant threat from data injection attacks – a category of cyberattacks that seeks to compromise system integrity, manipulate data, and breach security defenses.
Data injection attacks, also...
Group of researchers from UCSC are submitting a ChatGPT-4 designed and tested RISC-V 32-bit compliant crypto extension accelerator. All the designs and tests were written by ChatGPT-4 and were done in DSLX, a google-created High Level Synthesis language. DSLX uses a Rust-style syntax, making it easy for LLMs to understand given the wealth of...
This project is an Edge AI execution environment for running Meta's LLaMa2 and Code LLaMa on a Raspberry Pi 4 with 64-bit OS to automatically generate verilog code.
This is our submission for the EFabless AI Generated Chip Design Competition. It features a wishbone-accessible vector co-processor with 6 vector register files and 6 scalar register files. It supports floating point, boolean, integer, and scalar operations. Additionally it supports conditional vector instructions with predicate registers.