Efabless Repositories
Code hosting system for your Efabless projects
All Projects 573
jasteve4 / MicroMotorController-V3
Controller to manage up to 32 different half h-bridge at the some time.
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Apache-2.0
abdulmoizsheikh1 / Convolution_Accelerator_1
This project gives a implementation of a opensource convolution accelerator
The design has two sub designs
A convolution engine and a distributed control memory controller
The engine is intended to be a small in size low in power and performance optimized.
The project also contains a memory controller that works on distributed pipelined...
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Apache-2.0
alokerdas / Multi-core-embedded-SoC
This project has 10 16-bit microprocessors. Each of them is an Instruction Set Architecture CPU. Each CPU has its own private memory. Each memory is 512 words deep. Each word is 16 bits wide. Six CPUs are connected to the chip boundary. Each of them accesses 8 IOs. Four CPUs are connected to a serial protocol hub. The hub has 4 SPI modules, so,...
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Apache-2.0
prakharsingh39 / addressable_pixel
This projects consists of the design of a pixel consisting of individual RGB LED's which can be individually accessed through a bit pattern to generate the required colour.
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mathis / SoomRV-GFMPW1
The Linux-capable, out-of-order SoomRV rv32i core on GF180MCU
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Updated 11 months ago
mathis / SoomRV-GF180MCU
The Linux-capable, out-of-order SoomRV rv32i core on GF180MCU.
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Apache-2.0
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Updated 11 months ago
homelith / ishikai-gds-test-homelith
ishikai-gds-test-homelith
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Apache-2.0
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Updated 11 months ago
gonsolo / Diffuse_Shader
A simple diffuse shader as used in rendering applications, but this time hardwired in silicon.
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Apache-2.0
abdulmoizsheikh1 / Slick_Matrix_convolver
The project presents a area efficient implementation of a high speed matrix convolution engine. The engine has an integrated memory capable of storing the one matrix locally to avoid repeated off chip communication.
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Apache-2.0
mattmorrison / nd-mips8-efabless
Demo and Student Projects for Fall 2023 CSE 30342 Digital Integrated Circuits at the University of Notre Dame
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Apache-2.0
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Updated 11 months ago
yathag / AES
The Advanced Encryption Standard (AES) is a widely used symmetric encryption algorithm. This project focuses on a simplified implementation of AES on the GF180 Shuttle.
The AES hardware implementation is designed by Joachim Strömbergson at the following github repository.
https://github.com/secworks/aes
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Apache-2.0
urielcho / OQPSK_A_GFMPW1
The Asynchronous OQPSK Modulator, designed at CINVESTAV-IPN, offers efficient OQPSK modulation with asynchronous operation for adaptability in various digital communication applications.
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Apache-2.0
asinghani / multi_project_98154_course_mux
Multi-project submission including student designs from Fall 2023 CMU course 98-154 Intro to Open-Source Chip Design. This variant uses a hierarchical multiplexer similar to that used by early multi-project-harness
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Apache-2.0
andylithia / Seija
QDI Asynchronous Control-Add Logic Demo
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Apache-2.0
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Updated 11 months ago
kisek / rvcore_chip2
We are developing an optimized RV32I processor named RVCoreP, adopting five-stage pipelining targetting both FPGAs and ASICs. This project aims to evaluate our preliminary processor design regarding operating frequency and power consumption.
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Apache-2.0
egorxe / Ophelia_eFPGA_rerun
Uranus eFPGA with nonvolatile config in eFuse array. GFMPW1 rerun with fixes.
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Apache-2.0
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Updated 11 months ago
ranan / omotya
In my project, I designed a 10-bit SAR ADC. To accommodate digital inputs, I added a CDAC circuit to the input stage.
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Apache-2.0
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Updated 11 months ago
shahzaibk23 / Magma-Si
Hardware accelerator developed in CHISEL HDL specifically for accelerating Generic Matrix Multiply (GeMM) operations and is based on a Network on Chip architecture with generic bus interfaces. It contains 2 Dot Product Hardware Engines to compute the matrix multiplication and is 5.7x times faster than traditional systolic array based GeMM Accelerators.
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philippguehring / gf180_stdcelllib_1
This is a test chip which contains a bunch of digital logic cells that have been automatically layouted with Libresilicon's StdCellLib and have been directly connected to the IOs, so that you can use their logic functions directly:
INV, AOAAOI2124, MUX8, AAOAOI33111, AAAOAI3221, ASYNC3, AAOI22, AAAOI222, NAND4, AAAAOI3322, AAAOAOI33311, AAAOI333
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akaram / nd-cool-ranch
Our final project is an implementant of a Linear Shift Feedback Register (LSFR) in verilog.An LSFR acts as a pseudorandom number generator. SEE GITHUB
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Apache-2.0
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Updated 11 months ago
abdulmoizsheikh1 / Massive_Accelerator
This project gives a implementation of a opensource matrix convolution
The design has two sub designs
A convolution engine and a distributed control memory controller
The engine is intended to be a small in size low in power and performance optimized.
The project is presented to be highly parallelized and high in performance.
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Apache-2.0
scorbetta / CORTEZ1_GFMPW1
The `CORTEZ` design implements a simple Neural Network trained to recognize 3 vowels (`o`, `u` and `i`) represented as a 3x3 matrix.
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Apache-2.0
davidsimonetti / Mini_RSA_Encryption
Our project performs an RSA encryption of an 8-byte input and output the result. The public key used for encryption can also be changed.
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Apache-2.0
raymondmeng / Encryption_Algorithm
DES encryption & decryption
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Apache-2.0
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Updated 11 months ago
thorstenknoll / J1Asic_GF180
This is the reimplementation of a tiny stack based CPU, named J1. Stack based CPUs were used a lot but got forgotten in the past decades, mostly in combination with the language FORTH. This version of the J1 is stripped down to work with DFF RAM. A full J1 could run a complete FORTH system. Have you ever had a pocket calculator with reverse...
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Apache-2.0
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Updated 11 months ago
algofoogle / ztoa-team-group-caravel
Multiple muxed designs/experiments assembled by Zero to ASIC Course participants (GFMPW-1)
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Apache-2.0
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Updated 11 months ago
mrinverter / lfd111x_rvcore
Single Cycle (almost complete) RV32I written in TL-Verilog from LFD111x
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Apache-2.0
hishamelreedy / Advanced_Encryption_System_Accelerator_v1
Advanced Encryption System (AES) Accelerator
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Apache-2.0
hwuser0 / Simple_Filter_Design
Simple Design Implementation of FIR Low Pass Filter and Moving Average Filter
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Apache-2.0
aidanoblepias / parity-checker-nd-aagl
This repository contains the Verilog implementation of a signal parity checker designed to be synthesized on the EFabless Caravel OpenLane flow. The circuit is intended for use with the Global Foundries gf180mcuD Process Development Kit as part of the coursework for CSE 30342 - Digital Integrated Circuits at the University of Notre Dame.
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Apache-2.0
jamestimothymeech / Systolic-Array
This is a more advanced project built using the same method as: https://github.com/JamesTimothyMeech/RNG
The systolic array is a significantly more advanced design than the random number generator. We used GitHub Copilot with the random number generator design files open as reference to produce this more advance design in a single GitHub...
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Apache-2.0
asinghani / 98154_multiproject_HIER
Hierarchical version of 16 student designs from the course 98-154 Intro to Open Source Chip Design
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baungarten / nano_eFPGA
This project develop an eFPGA whit 2x2 CLB
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Apache-2.0
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Updated 11 months ago
jdgarci / gf180_sram_1kB_8x1024
1 kB SRAM made with OpenRAM.This memory has a word size of 8 bits and an total of 1024 words.This is a work of two, my friend Alfonso Lopez and I.
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Apache-2.0
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Updated 11 months ago
abdulmoizsheikh1 / Brute_Accelerator
This project gives a implementation of a convolution engine. The design has two sub designs A convolution engine and a distributed control memory controller The engine is intended to be a high performance low in power and highly parallelized. The project is hoped to give high performance than existing architectures.
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