Group efabless_staff - Efabless Repo

jdicorpo/2309_test_2

User flow test for 2309 shuttle.

yangd333/RX-Receiver_Frontend

Simple RF Receiver front-end for WiFi 6 (5.925 GHz). Aims to improve linearity on LNA and Mixer.

datnassoc/Data-Encryption-POC

Advanced Encryption in ASIC for Datacenters

jdicorpo/ogs_sensor

OGS Sensor

ryanmprice/UTEP_CML_Sensor_Test_Article_17

Convergent Microsystems Lab Test article for sensor interfaces

benisonpin/ISP_cteTWLCEO

Integrate the RISC-V & ISP pipeline

junchengchin/EESPFAL_PRESENT80_Round_1

To realize round one of lightweight hardware encryption PRESENT80 using Energy Efficient Secure Positive Feedback Adiabatic Logic (EESPFAL). The target is validation of functionality, low power consumption, and secure against side channel power analysis attacks. A traditional digital logic counterpart is incorporated for comparison.

samdlarson/test_chip_PV_231105

Packaged Version - Test Chip

engrvip/ssp_testchip

This is the first testchip containing designs from KACST-SSP students.

ac3e_chile_chipathon_team/AC3E_Open3LFCC_V2_repo

Open3LFCC_V2 and student projects

samdlarson/test_chip_B_231105

Bare Die Version - Test Chip

nicolas/arx

sha256

facundoaguirre/PUF_Design

Bistable Ring PUF

olyanasab/test_precheck_

test

ellenwood_siliconcontact/Silicon_Contact_3GBT

Silicon Contact has partnered with Siemens, Dycotec and MTC to create a 99% efficient drop in replacement for IGBT power transistors using "third generation" bipolar technology and a novel IC driver.

juansebastianmoya7/UNIC-CASS_precheck_IC3

Integration of the blocks AgroCHip, BGR_Temp, BLE, PLL_Uniandes, and PSCM

abouzeid/OSU_SMART

Test chip for crypto accelerators

burak_aykenar/SAKAv0.1

This is an embedded FPGA (eFPGA) IP project. The fabric netlist is generated by OpenFPGA framework. https://github.com/lnis-uofu/OpenFPGA This IP is designed by Yongatek Microelectronics. Yongatek Microelectronics provide a wide range of IC/ASIC/SoC/Chip Design, 5G/6G and Satellite Communications, Video Processing and IoT areas within the industry with an experienced and highly qualified R&D team. https://www.yongatek.com/ FPGA fabric consist of 6x6 complex logic blocks (CLB). Each CLB has 4 logic elements (LE). Each logic element has a LUT4 and a FF. Routing channels have 60 tracks: 6 L1, 6 L2 and 48 L4 track lengths. There are 24 IO blocks surrounding the fabric. Each IOB has 6 IO pins, a total of 144 pins. Pins are connected to logic analyzer (LA) of the management core and other 38 external IOs. You can contact through info@yongatek.com

rodrigowue/IC1-CASS-2023

IC1-CASS-2023

a_james/ReRAM_Crossbar

ReRAM crossbar Arrays for In-Memory Computing

monktech/Ka-Naada

One keyboard for many Indic languagesKa-Naada is a unique patented keyboard layout design for Indic languages (Brahmi based), without clutter and overload of English language feature of ‘spelling’.

monktech/Cientera

Space Microcontroller

monktech/Smowcode

Smowcode – An industry-grade visual coding language for ESP32 & MSPM0+ micro-controllers.

monktech/FuseEV

We combine new powertrains with classic car charm "Designing a classic car to run on electric is an art form and we aim to extend the life of your classic car by giving it a new sustainable lease of life"

dan20kim/Motion-Compensation-IC-v2

Motion Compensation IC

olyanasab/g.to1

g.to1 ADC+TX

masa/aisol_chip_1

aisol test chip 1

chompfish/ProbabilisticComputingAccelerator

A probabilistic computing accelerator.

yonguk/RRAM-Memory

RRAM: Resistive random access memory using sky130 ReRAM The memory includes a ReRAM array, decoder, sense amplifier, and controller. Mixed-signal designs -digital part: controller -analog part: others Features Forming Write Read

manishmahajan/LDPC_ENC_DEC

NR 5G 2_0_4 BG2

smay26/analog_tester2

tester

bernaorsyalcin/SoCwithRISCVandCDMAM

HSMs allow hardware implementation of cryptography algorithms with high performance and security. Especially finance, military, intelligence, health, etc. It is possible to meet the high speed requirement of security protocols that undertake critical tasks in sectors and work with large data widths, with algorithm-specific hardware (Custom IP). Although Custom IPs implemented as ASICs or on FPGAs for cryptography algorithms work much faster than software implementations of algorithms, a processor responsible for control and data communication with the outside world is used, and Custom IPs are connected to this processor and SoC is created. Since the data inputs and outputs required by cryptography algorithms are 4 to 128 times longer than the bus lengths of today's processors, when a system is created with Custom IPs directly connected to the processor, most of its time will be devoted to data transfer, so the system will not work efficiently. In this project, a special direct memory access module will be designed that will enable the transmission of commands and data over RAM between data ports such as PCIe, Custom IP and the processor using only the RAM interface of the RISCV processor. Using this designed module; As a high-speed HSM SoC, it will be implemented on FPGA, functional and performance tests and detailed verification will be made and the project will end with ASIC design, production and testing.

jocwcg/wcg_soc_2024

SoC with DSP accelerators

a_james/Reramcrosbar

Analog ciruitry

bharatpi/Bharat-Pi-Om

Risc V based MCU for tinkering labs and mini projects.

dancingquark/PWM

Project is about the pulse width multiplier

passant/SRAM-TC

Test chip for S8TSSC

passant/caravel-dft

Caravel with DFT in the SoC and user project wrapper

passant/caravel-dft-upw

Caravel DFT with AES user project wrapper from OL2 tutorial

passant/swift-V3

Swift redesign

qpwo/luke_chip

luke's chip

Efabless Staff

Group Projects