Group efabless_staff - Efabless Repo

marwan_abbas/caravel_mini_2411_antonVGA

Caravel Mini internal project. This project has Anton's VGA added to the counter, along with the default counter projects in the other 2 slots

jocwcg/wcg_2024

CINVESTAV WCG 2024

xingsmart/RRAM_1024x1024_array

RRAM Tapeout using sky130

amm_efabless/ci2411mini_demo_vga

Demo digital design for CI2411 chipIgnite mini, producing VGA output based on https://github.com/algofoogle/raybox-zero

antonfoogletest/AntonMaurovic-DocoTestOnly

AntonMaurovic-DocoTestOnly

pdlos/LC01

light clock chip

thomasjagielski/async_md5_hasher

Asynchronous md5 hasher.

amm_efabless/ci2411_vga3_counter

Resubmission of ci2409_counter_and_vga3 demo chip (counter example plus VGA demo)

samdlarson/test_chip_PV_231105

Packaged Version - Test Chip

antonfoogletest/AntonMaurovic-DocoTest2

AntonMaurovic-DocoTest2

amm_efabless/ci2411_vga4_counter

Upgraded version of ci2411_vga3_counter, using newer raybox-zero code with combo vec/reg SPI and other fixes.

samdlarson/test_chip_B_231105

Bare Die Version - Test Chip

rahulkumar/UCB-STACv2

University of California, Berkeley: SRAM Timing Analysis Chip version 2

amm_efabless/ci2411_7seg_alt_counter

Copy of ci2409_counter_7seg_alt, resubmitting as-is for CI2411.

ellenwood_siliconcontact/Silicon_Contact_3GBT

Silicon Contact has partnered with Siemens, Dycotec and MTC to create a 99% efficient drop in replacement for IGBT power transistors using "third generation" bipolar technology and a novel IC driver.

amm_efabless/ci2411_vga4a_counter

Variation of ci2411_vga4_counter, hardened with OpenLane 1 version 2024.04.22 and PDK bdc9412b3e468c102d01b7cf6337be06ec6e9c9a

marwan_abbas/caravel_mini_2411

caravel mini project for aggregating the user projects into one project

amm_efabless/ci2411_vga4b_counter

ci2411_vga4a_counter project modified to use user_clock2 for raybox-zero and wb_clk_i for counter

mainengineering/DelayLineAnalog

DelayLineAnalog

antonfoogletest/Anton-test-UW-scaling-fix

Fix for GDS scaling per https://repositories.efabless.com/a_aboulsaad/UW-EE437-SP24 (University of Washington)

elpidakrp/UW-elpida

UW-elpida

xingsmart/RRAM_sindhu

digital ip, TDC DAC and NOC tet structures

anton_corp_acct_2/anton_corp_acct_2-TEST

anton_corp_acct_2-TEST: Testing corporate accounts

chompfish/ProbabilisticComputingAccelerator

A probabilistic computing accelerator.

manishmahajan/LDPC_ENC_DEC

NR 5G 2_0_4 BG2

keysom_asic/Keysom-Butterfly

Keysom 11/24 tapeout 1

amm_efabless/ci2411_vga5_counter

Adding Wishbone access to rbzero registers in ci2411_vga4_counter

ellesraaijmakers/TUe-CharTests

TU/e characterization tests. Chip designed by Jelle Verest, Edgar van Megen and Elles Raaijmakers.

musabfarooq96/FIR_Imaging

FIR imaging using devices in CMOS.

lucamartis0035/Weights_mem

4096x32 memory

jeff/CS_Test_Project3

A test of the OpenLane 2 flow at CS.

jocwcg/wcg_soc_2024

SoC with DSP accelerators

bharatpi/Bharat-Pi-Om

Risc V based MCU for tinkering labs and mini projects.

passant/caravel-dft

Caravel with DFT in the SoC and user project wrapper

amm_efabless/EF_SRAMx48

Test chip with 48 instances of the 1024x32b EF_SRAM (192kBytes)

niks0091/ISC-RF-Controller

We are designing RISC V based ISC RF Controller which we consider as Phase-1 of the development0

passant/swift-V3

Swift redesign

qpwo/luke_chip

luke's chip

amm_efabless/Ludwig-Anton-LC1

Ludwig-Anton-LC1

mainengineering/TestProject

Test Project

cittapeout/FCNN

-

marchuerta/RREFLECT

A pathtracing accelerator meant to render full light composition scenes more accurately than traditional ray tracing.

mdomorfaruque007/usa-reram

usa-reram

juansebastianmoya7/UNIC-CASS_precheck_IC3

Integration of the blocks AgroCHip, BGR_Temp, BLE, PLL_Uniandes, and PSCM

aidanmedcalf/ci2406-fgcaptest-drc-test

ci2406-fgcaptes varac.5 DRC test

amm_efabless/Anton-Test-UCLA-Makar-2

Test upload for Makar from UCLA - Slot2

lrburle/Custom_Layout-Ring_Oscillators

This project consists of 10 custom layout ring oscillators that drive 5, 2-bit multiplier designs. These ring oscillators interface with Caravel-generated-mux16x1 designs to provide a selection system for all possible outputs. IO pads are set up to directly control the various 5 stages found within the ring oscillator(s) structure, multiplexer outputs, and the final outputs from the muxes.

bernaorsyalcin/SoCwithRISCVandCDMAM

HSMs allow hardware implementation of cryptography algorithms with high performance and security. Especially finance, military, intelligence, health, etc. It is possible to meet the high speed requirement of security protocols that undertake critical tasks in sectors and work with large data widths, with algorithm-specific hardware (Custom IP). Although Custom IPs implemented as ASICs or on FPGAs for cryptography algorithms work much faster than software implementations of algorithms, a processor responsible for control and data communication with the outside world is used, and Custom IPs are connected to this processor and SoC is created. Since the data inputs and outputs required by cryptography algorithms are 4 to 128 times longer than the bus lengths of today's processors, when a system is created with Custom IPs directly connected to the processor, most of its time will be devoted to data transfer, so the system will not work efficiently. In this project, a special direct memory access module will be designed that will enable the transmission of commands and data over RAM between data ports such as PCIe, Custom IP and the processor using only the RAM interface of the RISCV processor. Using this designed module; As a high-speed HSM SoC, it will be implemented on FPGA, functional and performance tests and detailed verification will be made and the project will end with ASIC design, production and testing.

amm_efabless/ci2409_counter_7seg_alt

Modified ci2409_counter_7seg to support output switching to alternate outputs (including all 4 hex digits)

engrvip/ssp_testchip

This is the first testchip containing designs from KACST-SSP students.

amm_efabless/ci2409_counter_7seg

Caravel test project from caravel_user_project with 7seg decoder added.

abouzeid/OSU_SMART

Test chip for crypto accelerators

mayankv/Mirafra_FPU

FPU design implemented by Mirafra Team

ryanmprice/VapidQuickMini

Quick integration of latest versions of softcore for silicon testing

asmamohsin997/FPGAIGNITE2024

This is a Multi Project Die (MPD) submission which contains designs created during the FPGA Ignite Summer School 2024 at Heidelberg University. The designs include a VGA driver with a Pixel Processing Unit (PPU) (FPGAIgnite-VGA), a random number generator (THE RING), an application-level posit capable RISC-V core (PERCIVAL) and a RISC-V eFPGA with custom instruction extensions (CXBex). All designs are connected to an eFPGA created using the FABulous Framework.

a_aboulsaad/UW-EE437-SP24

This is a capstone course project led by Professor Jacques C. Rudell, along with the PhD candidate Ahmed R. Aboulsaad. The tape-out chip will include 4 projects designed by undergraduate students and graduate students: 1- Quantum Controller Receiver Project. 2- Audio Amplifier Project. 3- Bi-directional Wireline Chip Interface Project. 4- High Linearity N-Path Filter Project.

niorcasitas07/UNIC-CASS_Ring_Oscillators

This repository includes the files related to the proposal entitled ‘Ring Oscillators Frequency degradation for Reliability characterization with Bias temperature instability (BTI) and hot carrier (HC) effects’ for UNICASS 2024.

elamdf/EECS151T

placeholder- undergrad-run educational SoC tapeout

amm_efabless/ci2409_test

Jeff's https://github.com/jeffdi/ci2409_test/ based on caravel_user_project

vonbraunlabs/vbl-riscv-slx

von Braun Labs - RISCV

a_james/Reramcrosbar

Analog ciruitry

passant/SRAM-TC

Test chip for S8TSSC

burak_aykenar/SAKAv0.1

This is an embedded FPGA (eFPGA) IP project. The fabric netlist is generated by OpenFPGA framework. https://github.com/lnis-uofu/OpenFPGA This IP is designed by Yongatek Microelectronics. Yongatek Microelectronics provide a wide range of IC/ASIC/SoC/Chip Design, 5G/6G and Satellite Communications, Video Processing and IoT areas within the industry with an experienced and highly qualified R&D team. https://www.yongatek.com/ FPGA fabric consist of 6x6 complex logic blocks (CLB). Each CLB has 4 logic elements (LE). Each logic element has a LUT4 and a FF. Routing channels have 60 tracks: 6 L1, 6 L2 and 48 L4 track lengths. There are 24 IO blocks surrounding the fabric. Each IOB has 6 IO pins, a total of 144 pins. Pins are connected to logic analyzer (LA) of the management core and other 38 external IOs. You can contact through info@yongatek.com

vonbraunlabs/vbl_riscv_slx

von Braun Labs RISC-V

dancingquark/PWM

Project is about the pulse width multiplier

naina/Volt_Technology_Efabless_CI2406

This project involves the IC design and fabrication conducted by Volt Technology, based in Auckland, New Zealand utilizing the SKY130 Process Design Kit (PDK).

amm_efabless/Anton-Test-UCLA-Makar-1

Test upload for Makar from UCLA - Slot1

datnassoc/Data-Encryption-POC

Advanced Encryption in ASIC for Datacenters

vonbraunlabs/vbl-riscv-ci2406

VBL RISC-V

tbeechem/SpecereThermVeh

This is a thermal test vehicle designed to assess optical thermometry methods and their applicability to logic.

christoph/ScoooterDexie

A security hardened RISC-V processor.

forks/amm_efabless/marchuerta/RREFLECT_efabless

A pathtracing accelerator meant to render full light composition scenes more accurately than traditional ray tracing.

ryanmprice/UTEP_CML_Sensor_Test_Article_17

Convergent Microsystems Lab Test article for sensor interfaces

rodrigowue/IC1-CASS-2023

IC1-CASS-2023

passant/caravel-dft-upw

Caravel DFT with AES user project wrapper from OL2 tutorial

amm_efabless/ci2409_counter_and_vga2

Revert to earlier version of ci2409_counter_and_vga with better timing

dan20kim/Motion-Compensation-IC-v2

Motion Compensation IC

amm_efabless/ci2409_counter_and_vga3

Anton's Efabless example project: counter example + VGA "raybox-zero" demo

ymei/SNRLxP0

SNRLxP0 chip for efabless tapeout in sky130

benisonpin/ISP_cteTWLCEO

Integrate the RISC-V & ISP pipeline

a_james/ReRAM_Crossbar

ReRAM crossbar Arrays for In-Memory Computing

damor_rbz/AGANTItp0

AGANTIv0

olyanasab/g.to1

g.to1 ADC+TX

yangd333/RX-Receiver_Frontend

Simple RF Receiver front-end for WiFi 6 (5.925 GHz). Aims to improve linearity on LNA and Mixer.

yonguk/RRAM-Memory-2409

Memory using sky130 RRAM

monktech/Ka-Naada

One keyboard for many Indic languagesKa-Naada is a unique patented keyboard layout design for Indic languages (Brahmi based), without clutter and overload of English language feature of ‘spelling’.

ac3e_chile_chipathon_team/AC3E_Open3LFCC_V2_repo

Open3LFCC_V2 and student projects

monktech/Cientera

Space Microcontroller

duwe/ChipForgeFrame

Silicon proving frame for Chip Forge projects.

monktech/Smowcode

Smowcode – An industry-grade visual coding language for ESP32 & MSPM0+ micro-controllers.

monktech/FuseEV

We combine new powertrains with classic car charm "Designing a classic car to run on electric is an art form and we aim to extend the life of your classic car by giving it a new sustainable lease of life"

jdicorpo/2309_test_2

User flow test for 2309 shuttle.

jdicorpo/ogs_sensor

OGS Sensor

mainengineering/DelayLine

Delay Line Test in Caravel

kevinwguan/ReRAM-Crossbar-Array

ReRAM-Crossbar-Array

federico_hyo/aVLSI2024

NeuromorphicClassChip

pdlos/Clock-Chip

Clock-Chip

anirudhgha/lc_architecture1

lc_architecture1

masa/aisol_chip_1

aisol test chip 1

dkong/Matmul_Kernel

matmul kernel with SRAM

yonguk/RRAM-Memory

RRAM: Resistive random access memory using sky130 ReRAM The memory includes a ReRAM array, decoder, sense amplifier, and controller. Mixed-signal designs -digital part: controller -analog part: others Features Forming Write Read

olyanasab/test_precheck_

test

amm_efabless/CUP_decap_test

Testing default decap cell behaviour with precheck/tapeout on Platform

smay26/analog_tester2

tester

efabless_common/snappy_tapeout

Snappy Project Tapeout

junchengchin/EESPFAL_PRESENT80_Round_1

To realize round one of lightweight hardware encryption PRESENT80 using Energy Efficient Secure Positive Feedback Adiabatic Logic (EESPFAL). The target is validation of functionality, low power consumption, and secure against side channel power analysis attacks. A traditional digital logic counterpart is incorporated for comparison.

nicolas/arx

sha256

facundoaguirre/PUF_Design

Bistable Ring PUF

manishmahajan/LDPC_5G

LDPC Encoder Decoder

Efabless Staff

Group Projects