LDPC_5G

LDPC Encoder Decoder

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Instructions

Local Project Setup - Git Commands

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git clone ssh://git@repositories.efabless.com/manishmahajan/LDPC_5G.git
cd LDPC_5G
... do some changes
git push -u origin main

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git remote add origin ssh://git@repositories.efabless.com/manishmahajan/LDPC_5G.git
git pull origin main --rebase --allow-unrelated-histories
git push -u origin main

If you already have a remote repository, for example one on GitHub, use the Git command below to add another remote Git repo (make sure that each repo has its unique ID, e.g. origin, ef-repo in the example below).

git remote add ef-repo ssh://git@repositories.efabless.com/manishmahajan/LDPC_5G.git
git push -u ef-repo main --force

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This is a LDPC Project for 5g lower matrix

LDPC_Project

LDPC Project is a sample smaller version of the design that is optimized using a SRAM to have low area. This increases the simulation time, as every iteration takes more number of clocks to do one step at a time, but it is still fast enough to correct errors. There is 4ms delay for sequential decoding with 13 iterations to converge at 40MHz. each iteration is 310,516,666ps there are 13 iterations 4,081,550,000ps for convergence at 40MHz. encoding 790,475,000ps to encode the code-word at 40MHz. Encoding takes 0.8ms to encode at 40MHz. This time is fixed for any code-word. It takes 4ms to complete the task of correcting errors for a LDPC(208,168,40) codeblock at clock frequency of 40MHz.

Synthesis runs at 20 KHz for 13um

Typically the code converges from 8 to 12 iterations. With implementatio using SRAMS the area utilization is lower SRAMS LDPC Design takes 12421 clock ticks per iteration For parallel LDPC Design it takes 23 clock per iteration The area utilization is higher in parallel LDPC design. This design can operate at very high frequency clocks.

The design for 5 clocks per iteration, with upto maximum required loops of 12 the number of clocks required are 60 clocks, at a clock which can be as fast as 1.2 GHz or more.

The slower design is for proof of concept, though can be used for 5G. For 6G the same matrices can be used with the faster design to get high throughput.

The matrices for 5G,6G are...

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ENV setup

env.bash env.tcsh

Project Structure

module git@github.com:manish03/LDPCENCDEC.git sub modules: git@github.com:rggen/rggen-verilog-rtl.git git@github.com:mattvenn/openlane_summary.git git@repositories.efabless.com:manishmahajan/LDPC_ENC_DEC.git

Simulation can be run using the script

LDPCENCDEC/run.sh

For Synthesis use the script

Makefile in LDPCENCDEC/openlane/

ip_files

are present in the LDPCENCDEC/verilog/rtl directory.

design files

are present in LDPCENCDEC/verilog/rtl/LDPC_ENC_DEC directory

NOTE: Current design file examples are provided for initial reference. These files are currently being updated and will be reposted once complete. The simulations are working, gds has been created successfully.

C Program sample

A C program with an example for stimulus which will be encoded, error insertion and decoding has been provided at LDPCENCDEC/verilog/dv/wb_port/wb_port.c