burak_aykenar
Burak a • Joined 2 years ago
Projects
2 Projects
burak_aykenar/SAKAv0.1
This is an embedded FPGA (eFPGA) IP project. The fabric netlist is generated by OpenFPGA framework.
https://github.com/lnis-uofu/OpenFPGA
This IP is designed by Yongatek Microelectronics. Yongatek Microelectronics provide a wide range of IC/ASIC/SoC/Chip Design, 5G/6G and Satellite Communications, Video Processing and IoT areas within the industry with an experienced and highly qualified R&D team.
https://www.yongatek.com/
FPGA fabric consist of 6x6 complex logic blocks (CLB). Each CLB has 4 logic elements (LE). Each logic element has a LUT4 and a FF. Routing channels have 60 tracks: 6 L1, 6 L2 and 48 L4 track lengths.
There are 24 IO blocks surrounding the fabric. Each IOB has 6 IO pins, a total of 144 pins. Pins are connected to logic analyzer (LA) of the management core and other 38 external IOs.
You can contact through info@yongatek.com
burak_aykenar/YONGA-MCU
Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C.
The design is based on famous pulp team's pulpino. We (Yongatek Microelectronics from Turkiye) try to tape-out this MCU to gain experience on openlane flow with MPW7 with minor modifications from the original pulpino work. You can get more information about pulp team and pulpino by clicking links below:
PULP Platform https://pulp-platform.org/index.html
Pulpino SoC https://github.com/pulp-platform/pulpino
Our main aim is to add our previous MPW submissions such as CAN, MODBUS and Ethernet to YONGA-MCU by modifying and enhancing it and tape-out in MPW8 our final MCU system.