jdicorpo
Jeff DiCorpo • Joined 5 years ago
Projects
100 Projects
jdicorpo/2309_test
The is a test project for CI 2309.
jdicorpo/2309_test_2
User flow test for 2309 shuttle.
jdicorpo/2309_test_3
Test project.
jdicorpo/2311_test
Test project
ac3e_chile_chipathon_team/AC3E_Open3LFCC_V2_repo
Open3LFCC_V2 and student projects
damor_rbz/AGANTItp0
AGANTIv0
smay26/analog_tester2
tester
amm_efabless/Anton-Test-UCLA-Makar-1
Test upload for Makar from UCLA - Slot1
amm_efabless/Anton-Test-UCLA-Makar-2
Test upload for Makar from UCLA - Slot2
antonfoogletest/Anton-test-UW-scaling-fix
Fix for GDS scaling per https://repositories.efabless.com/a_aboulsaad/UW-EE437-SP24 (University of Washington)
thomasjagielski/async_md5_hasher
Asynchronous md5 hasher.
bharatpi/Bharat-Pi-Om
Risc V based MCU for tinkering labs and mini projects.
jdicorpo/Blizzard
Blizzard project
passant/caravel-dft
Caravel with DFT in the SoC and user project wrapper
passant/caravel-dft-upw
Caravel DFT with AES user project wrapper from OL2 tutorial
marwan_abbas/caravel_mini_2411
caravel mini project for aggregating the user projects into one project
jdicorpo/caravel_openframe_project
Example project demonstrating the use of caravel openframe.
chipignite/caravel_user_project
Caravel User Project provides a template for implementing designs using Caravel compatible with chipIgnite.
chipignite/chipignite-project4
chipignite-project4
chipignite/chipignite-project9
chipignite-project9
chipignite/chipignite-start-00
chipignite-start-00
aidanmedcalf/ci2406-fgcaptest-drc-test
ci2406-fgcaptes varac.5 DRC test
jdicorpo/ci2406_test
Test project
amm_efabless/ci2409_counter_7seg
Caravel test project from caravel_user_project with 7seg decoder added.
amm_efabless/ci2409_counter_7seg_alt
Modified ci2409_counter_7seg to support output switching to alternate outputs (including all 4 hex digits)
amm_efabless/ci2409_counter_and_vga2
Revert to earlier version of ci2409_counter_and_vga with better timing
amm_efabless/ci2409_counter_and_vga3
Anton's Efabless example project: counter example + VGA "raybox-zero" demo
amm_efabless/ci2409_test
Jeff's https://github.com/jeffdi/ci2409_test/ based on caravel_user_project
amm_efabless/ci2411_7seg_alt_counter
Copy of ci2409_counter_7seg_alt, resubmitting as-is for CI2411.
amm_efabless/ci2411mini_demo_vga
Demo digital design for CI2411 chipIgnite mini, producing VGA output based on https://github.com/algofoogle/raybox-zero
amm_efabless/ci2411_vga3_counter
Resubmission of ci2409_counter_and_vga3 demo chip (counter example plus VGA demo)
amm_efabless/ci2411_vga4a_counter
Variation of ci2411_vga4_counter, hardened with OpenLane 1 version 2024.04.22 and PDK bdc9412b3e468c102d01b7cf6337be06ec6e9c9a
amm_efabless/ci2411_vga4b_counter
ci2411_vga4a_counter project modified to use user_clock2 for raybox-zero and wb_clk_i for counter
amm_efabless/ci2411_vga4_counter
Upgraded version of ci2411_vga3_counter, using newer raybox-zero code with combo vec/reg SPI and other fixes.
amm_efabless/ci2411_vga5_counter
Adding Wishbone access to rbzero registers in ci2411_vga4_counter
monktech/Cientera
Space Microcontroller
jeff/CS_Test_Project3
A test of the OpenLane 2 flow at CS.
amm_efabless/CUP_decap_test
Testing default decap cell behaviour with precheck/tapeout on Platform
datnassoc/Data-Encryption-POC
Advanced Encryption in ASIC for Datacenters
jdicorpo/datnass_mvp
Encryption for datacenter
jdicorpo/datnass_poc
PoC for encryption on the go
jdicorpo/demo_5
this is a demo project
jdicorpo/doc_test
repo to test documentation rendering
elamdf/EECS151T
placeholder- undergrad-run educational SoC tapeout
amm_efabless/EF_SRAMx48
Test chip with 48 instances of the 1024x32b EF_SRAM (192kBytes)
musabfarooq96/FIR_Imaging
FIR imaging using devices in CMOS.
asmamohsin997/FPGAIGNITE2024
This is a Multi Project Die (MPD) submission which contains designs created during the FPGA Ignite Summer School 2024 at Heidelberg University. The designs include a VGA driver with a Pixel Processing Unit (PPU) (FPGAIgnite-VGA), a random number generator (THE RING), an application-level posit capable RISC-V core (PERCIVAL) and a RISC-V eFPGA with custom instruction extensions (CXBex). All designs are connected to an eFPGA created using the FABulous Framework.