Efabless Repositories
Code hosting system for your Efabless projects
All Projects 574
yangd333 / RX-Receiver-Frontend
RF Receiver front-end for WiFi 6 (5.925 GHz).
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Updated a year ago
muhammadmustafa / 4-input-8-bit-Comparator
This is a very small part of my FYP, working under the Mentorship of Prof. Dr. Attiya Baqai, as a student. The main idea is to connect the inputs with ADCs and take pressure data and the highest pressure would be shown on the output. The application is of plantar pressure device on a small scale.
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a_james / Sigmoid_1
Verilog implementation of Sigmoid function using Zhang approximation
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wangxinze / Cyberrio
A RISC-V five-level pipeline CPU core dominated by GPT-4
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jeetsumanto123 / Bloom-Filter-Counter(AI-Generated-Design)
"In the context of the Bloom Filter Counter, we adapt the Bloom filter concept to create a probabilistic counter. Instead of testing for set membership, we utilize the Bloom filter to track the occurrence of unique elements. The counter increments based on the presence or absence of an input data element in the Bloom filter."
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Updated 8 months ago
asinghani / CMU-18-224-Student-Projects
Student-submitted designs in the 18-224/624 Intro to Open Source Chip Design class at Carnegie Mellon University
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aidanmedcalf / sky130-sonos-test
SONOS test array + additional test circuits
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passant / LDO1V8
A test chip including three 3.3 V to 1.8 V, 100 mA, LDO
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passant / Clear
CLEAR is an Open Source FPGA-ASIC utilizing 9x9 eFPGA
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passant / MPC4
Multi-Project Caravel (MPC): The user’s project area is partitioned into 4 (2x2) small projects of 1.3x1.6mm2 each. The current layout integrates 4 different counters.
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martinsauter / Test-Structures-for-BJTs
We designed a couple of teststructures for electrical characterisation of bipolar transistors in the Sky130A process. Test structures can be accessed by conventional microprobes via pads.
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dan20kim / Motion-Compensation-IC
This is the motion compensation block of a hardware video CODEC system.
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deepak / SRAM_IMC_MPW8
SRAM in memory computing : The project includes SRAM In Memory Computing Accelerator. This is the updated version of our previous submission.
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amifsud / mega4_reram_splits
A replica of the nominal project with a significant difference - main objective is characterising different sweeps/splits of ReRAM devices (4 shapes - square, rect, hex, circle & multiple sizes - dimensions range between 0.23um to 1.25um). This way we can derive the relationship between these parameters and its characteristics to enable...
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mattvenn / Zero-to-ASIC-course-group-submission-for-MPW8
Zero to ASIC course group submission for MPW8
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amifsud / mega4_reram_nom
An aggressively designed core ReRAM cell with a pitch of 1.08um x 1.56um. The main objective is characterising (IV, retention, endurance, etc) the 'standard' ReRAM cell including variability, and yield information.
Top level; A 1T1R ReRAM array with 4 million cells, row and column decoders, and an analog output.
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carllb / Mixed_signal_circuits_MPW8_Dec14
We are planning to make a Mixed signal in-memory compute ReRAM arrray. This takeout will allow us to measure the performance of the ReRAM devices and other analog and mixed signal devices.
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pattrs12 / divider
This is a clock divider of 2, 4, 8, 16, 32, 64, 128, 256, 512, and 1024.
This project will help us test the gf180 technology at CINVESTAV in Guadalajara, Mexico.
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aashishiiitb / iiitb_alu
Arithmatic Logic Unit
ALU is a processor unit which performs the task of addition, subtraction, multiplication, and division. In order to support CPU for its arithmatic and logical processes, ALU has AU (i.e) arithmatic unit and LU (i.e) Logical Unit. This paper deals with its analysis and functioning of this important unit of CPU using...
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asinghani / Stu154-F22-Student-Projects
A group submission including several small designs contributed by students at Carnegie Mellon in Open Chip Design StuCo, and some designs for demo purposes.
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kozmik / CollatzGF180
Small Test Digital Project that calculates the orbit of a N number using the Collatz Conjecture
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egorxe / Ophelia-eFPGA
Uranus eFPGA with nonvolatile config in eFuse array.
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Updated 11 months ago
chithambaramoorthii / RRAM_IMC_V2_FLAT
In Memory computing RRAM accelerator.
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urish / Game-of-Life-Cell
Implements the logic of a single game of life cell
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asgaris / Low-Power-Scalable-Mixed-Signal-SoC-DNA-Sequencing
Nanopore-based DNA sequencing is a unique, scalable technology, utilized to identify nucleotides (i.e., A, C, G, T) according to the pico-ampere-sized current fluctuations induced by the passage of a DNA strand through a like-sized molecular sensor (i.e., a “nanopore”). This approach, a so-called “3rd Generation” sequencing technology,...
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Updated 8 months ago
skandhadeepsita / Energy-Efficient-Sum-of-Products-circuit
The sum of products circuits with four 8-bit inputs, approximate multiplier and approximate adder elements and 17 bit output with function Z=AB+CD
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Updated 7 months ago
skandhadeepsita / Approximate-Adder-AXHA
This project is an implementation of approximate adder for error tolerant multimedia applications.
The approximate single bit adder is built using which multi bit adder is built basing on the approximation factor. The delay chain is completely eliminated for the approximate part and is reduced by length k for accurate half of the n-bit...
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Updated 7 months ago
hpretl / SAR-ADC-and-Digital-Temperature-Sensor
We have implemented mixed signals blocks: A SAR-ADC with 12b and OSR=1...256 (decimation filter included), and a fully synthesizeable digital temperature sensor
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praneeth / IIITDMK_16-point-Walsh-Transform
Implementing the matrix operation of 16-point Walsh Transform using 8-bit inputs.
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mathis / SoomRV-(MPW-8)
SoomRV testing resubmission for MPW-8!
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Updated 11 months ago
ryanmprice / EduWave
Experimental Digital Process Blocks for Incomplete PDK
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alisabir4121 / SSCS2-PICO-CHIP-1
This submission is a merger of the following SSCS PICO Projects.
1. DC-DC converter
https://github.com/Jawad1316/DC-DC-Converter-Chipathon.git
2. Sigma Delta (SD)
https://github.com/i212431/SPATIAL_SD_ADC.git
3. Matrix Multiplier
https://github.com/shaheer777/MATRIX-MULTIPLIER-FOR-AI-ON-EDGE-APPLICATIONS.git
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anizam / SSCS-PICO-Chip-7
USA 5 group from University of Tennessee Knoxville designing an Electrochemical Sensor chip to monitor water quality.
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ac3e_chile_chipathon_team / SSCS-PICO-Chip-6
This submission is a merger of the following SSCS PICO Projects.
https://platform.efabless.com/projects/881
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Updated 12 months ago
huertam / NanoCMOS
A single-photon resolution color imager chip
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chithambaramoorthii / In-memory-computing-RRAM
The project includes RRAM In Memory Computing Accelerator, by researchers mentioned below under the supervision of Prof: Manan Suri (NVM & Neuromorphic Hardware Research Group IIT-Delhi, https://web.iitd.ac.in/~manansuri/)
Ayan Ray,
Chithambara Moorthii J,
Vivek Parmar
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Updated 10 months ago
deepak / In-memory-computing-SRAM
SRAM in memory computing : The project includes SRAM In Memory Computing Accelerator.
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mathis / SoomRV
SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute 4 Instructions per cycle completely out of order, and also supports speculative execution and precise exceptions.
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burak_aykenar / YONGA-MCU
Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C.
The design is based on famous pulp team's pulpino. We (Yongatek Microelectronics from Turkiye) try to tape-out this MCU to gain experience on openlane flow with MPW7 with minor modifications from the original pulpino work. You can...
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abdullahyildiz / YONGA-CAN-Controller
YONGA-CAN Controller is a partial implementation of CAN 2.0B standard.
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